At 27/09/06 21:05, Brian Guralnick wrote: > Ok, my last PCB for the first time I used true power planes. I noticed >that unconnected pads/vias on the plane layers had no copper pad to them, >they were blank hole allowing for the power plane to fill more completely >where there may be many vias in a cramped space. > > Is there a way to setup the PCB design rules so that the polygon fills >create the same effect for the unconnected vias & pads.
Afaik, no. What's the use anyway? This would seem to serve no other purpose than to increase the impedance of the plane (larger holes = less copper) and to increase the parasitic capacitance between the unconnected vias and the plane, neither of which is desirable (at least, in my designs). Unless, of coarse, you have the planes on the outside of the PCB (and even then the above still applies). In which case I would use a polygon with grid = 0.... BTW, the gap between the barrel (plated hole) of the via and the plane is controlled by a rule under manufacturing. Just in case you missed it.... Leo ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
