Can the latest Altium release perform my requires task? This would get me to buy it, I would save humungo on a current 12 layer 3 drill file PCB, going down to 10 layers, 2 drill files.
____________ Brian G. ----- Original Message ----- From: "Leo Potjewijd" <[EMAIL PROTECTED]> To: "Protel EDA Discussion List" <[email protected]> Sent: Wednesday, September 27, 2006 6:46 PM Subject: Re: [PEDA] P99se, Unconnected vias in the middle of a polygon fill. > At 27/09/06 23:52, you wrote: >> > Afaik, no. What's the use anyway? >> > This would seem to serve no other purpose than to increase the >> > impedance of the plane (larger holes = less copper) >> > Leo >> >>I think you might have thing backwards, or, misunderstoo what I >>really want to do. > > You're right, I had it backwards. Silly me. > I once had a design that relied on the top and bottom layers for its > ground plane (it had vias every 150 mils), but after the first > proto's were EMC tested I quickly added an internal ground plane and > ended up with a six-layer board..... > >> For example: > > Okokok, I understand what you're trying to do. ;) > >>snippety-snip > > Just an observation: on my designs the measurements you gave are > considered "humongous" ;) > The only way I can think of to achieve what you want is making the > via size equal to the hole size (with matching DRC rules of course) > and manually put the required copper on the layers where needed, a > sort of DIY padstack... > This will probably result in a) the wanted result and b) a complete > nightmare if you ever have to change the location of even one of > those vias. Maybe the nightmare will revert to 'only' a bad dream if > you create library parts that will do this, but it will remain > troublesome. Blind vias are no option, I gather.... > > Good luck, 'for this is no easy task'. > Good night even, I'm off to bed. > > Leo Potjewijd > hardware designer > > Integrated Engineering > Paasheuvelweg 20 > NL-1105 BJ Amsterdam Zuidoost > The Netherlands > T: +31 20 4620713 > F: +31 20 4620756 > E: [EMAIL PROTECTED] > I: www.smart-ID.com > > Integrated Engineering USA > > West coast > PO Box 32 - Carmel Valley > CA 93924 United States of America > T: +1 831 659 3218 > F: +1 831 659 1009 > > East Coast > PO Box 151 > 490 Kinderhook Rd > Columbia, PA 17512 > T: (717) 666-1107 > F: (717) 666-1116 > > This E-Mail message is intended only for the use of the individual or > entity to which it is addressed and may contain information that is > privileged, confidentional and exempt from disclosure. > If the reader of this E-mail message is not the intended recipient, > you are hereby notified that any dissemination, distribution or > copying of this communication is strictly prohibited. If you have > received this communication in error, please notify us immediately by > telephone on +31 (0)20 4620 755. Thank you for your co-operation. > > > > ____________________________________________________________ > You are subscribed to the PEDA discussion forum > > To Post messages: > mailto:[email protected] > > Unsubscribe and Other Options: > http://techservinc.com/mailman/listinfo/peda_techservinc.com > > Browse or Search Old Archives (2001-2004): > http://www.mail-archive.com/[email protected] > > Browse or Search Current Archives (2004-Current): > http://www.mail-archive.com/[email protected] > ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[email protected] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
