Robert Gillatt wrote:
> and I haven't found a way to >create test vectors for logic circuits. It may be possible using a ROM model >but the whole process looks too grisly for words. > > > SPICE is an awful way to do logic simulation. If you are doing transistor level modelling of chip internals, it makes sense. If you have a logic schematic using a bunch of misc. chips, it just slows to an absolute crawl. There are very good logic simulators that work. ModelSim is part of the Xilinx CPLD/FPGA suites, and although I don't like their GUI much, the logic simulation works fine, and must be 10,000 times faster than SPICE. Jon ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[EMAIL PROTECTED] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
