Tom Robinson wrote:
>A pesky clock signal on my board. Any tips on ways to route a clock signal on >a multilayer board. > >All in an attempt to minimize radiated emissions. > >Any and all help will be appreciated. > > Series termination at the source? Route on a signal layer buried between power/ground planes? Keep it as short and direct as possible. Keep it away from any lines that go to external connectors. That's the few things I know to do. Jon ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[EMAIL PROTECTED] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
