David Cary wrote:
>Dear Tom Robinson, > >... > > >>Any tips on ways to route a clock signal on a multilayer board. >> >> >... > > >>to minimize radiated emissions. >> >> > >Jon Elson gives the most important tips. >I have been collecting similar tips at the "Avoiding Noise" web page. > >However, Atmel's "EMC Design Considerations" paper seems to contradict >the "use power/ground as outer shields" idea: >"When... four or more layers are used ... one plane is used as a >ground plane... one layer as a power plane ... These two planes should >then be placed next to each other in the middle of the board, to >reduce power supply impedance and loop area. It is not a good idea to >place the power and ground planes as the outer layers to act as >shields. It does not work as intended, as high currents are running in >the ground plane." > > Yes, this is one of those tradeoffs. I always place the power and ground together for the lowest impedance of the planes, and have not used the buried/stripline traces for EMI supression. It depends on how much each of these conditions is a problem that MUST be solved. It may be required in some cases to trade off a little power plane noise to satify an EMI requirement. You can also add a shield plane, either over the whole board, or just as a local shield that covers the noisy trace, with lots of "stitch" vias to tie it to the main ground plane. There is no ONE answer to this, it totally depends on the specific requirements. Jon ____________________________________________________________ You are subscribed to the PEDA discussion forum To Post messages: mailto:[email protected] Unsubscribe and Other Options: http://techservinc.com/mailman/listinfo/peda_techservinc.com Browse or Search Old Archives (2001-2004): http://www.mail-archive.com/[EMAIL PROTECTED] Browse or Search Current Archives (2004-Current): http://www.mail-archive.com/[email protected]
