Brendan Miller <catph...@catphive.net> writes: > I'm curious about that. I've been looking around for timing > information on the lock signal, but am having some trouble finding > them. Intuitively, given that the processor is much faster than the > bus, and you are just waiting for processor to complete an addition or > comparison before put the new memory value on the bus, it seems like > there should be very little additional bus contention vs a normal add > instruction.
The bus is slow compared with the L1 cache. I just looked for figures and couldn't find any either, but I remember seeing some for the Core 2 saying around 100 cycles, and something similar for the Athlon. I just came across something saying the Core i7 is considerably better than the Core 2 at this. The real solution is to not use so much bus locking. Get rid of the ref counts and use a real gc, if not in CPython then in PyPy. -- http://mail.python.org/mailman/listinfo/python-list