From: Lucjan Bryndza <lbryndza....@icloud.com>
The current implementation of timers does not work properly
even in basic functionality. A counter configured to report
an interrupt every 10ms reports the first interrupts after a
few seconds. There are also no properly implemented count up an
count down modes. This commit fixes bugs with interrupt
reporting and implements the basic modes of the counter's
time-base block.
Add update egr function
Signed-off-by: Lucjan Bryndza <lbryndza....@icloud.com>
---
hw/timer/stm32f2xx_timer.c | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c
index 3997521610..010b5b41bd 100644
--- a/hw/timer/stm32f2xx_timer.c
+++ b/hw/timer/stm32f2xx_timer.c
@@ -233,6 +233,21 @@ static void stm32f2xx_update_psc(STM32F2XXTimerState *s,
uint64_t value)
ptimer_transaction_commit(s->timer);
DB_PRINT("write psc = %x\n", s->tim_psc);
}
+
+static void stm32f2xx_update_egr(STM32F2XXTimerState *s, uint64_t value)
+{
+ s->tim_egr = value & 0x1E;
+ if (value & TIM_EGR_TG) {
+ s->tim_sr |= TIM_EGR_TG;
+ }
+ if (value & TIM_EGR_UG) {
+ /* UG bit - reload */
+ ptimer_transaction_begin(s->timer);
+ ptimer_set_limit(s->timer, s->tim_arr, 1);
+ ptimer_transaction_commit(s->timer);
+ }
+ DB_PRINT("write EGR = %x\n", s->tim_egr);
+}
static void stm32f2xx_timer_write(void *opaque, hwaddr offset,
uint64_t val64, unsigned size)
{
--
2.38.5
