Re: [PATCH 05/13] target/riscv: Conceal MO_TE within gen_load() / gen_store()

[Alistair Francis]

On Sat, Oct 11, 2025 at 1:57 AM Philippe Mathieu-Daudé
<phi...@linaro.org> wrote:
>
> All callers of gen_load() / gen_store() set the MO_TE flag.
> Set it once in the callees.
>
> Signed-off-by: Philippe Mathieu-Daudé <phi...@linaro.org>

Reviewed-by: Alistair Francis <alistair.fran...@wdc.com>

Alistair

> ---
>  target/riscv/insn_trans/trans_rvi.c.inc   | 24 ++++++++++++-----------
>  target/riscv/insn_trans/trans_rvzce.c.inc |  6 +++---
>  2 files changed, 16 insertions(+), 14 deletions(-)
>
> diff --git a/target/riscv/insn_trans/trans_rvi.c.inc 
> b/target/riscv/insn_trans/trans_rvi.c.inc
> index 8194ea5073e..8db3e78baab 100644
> --- a/target/riscv/insn_trans/trans_rvi.c.inc
> +++ b/target/riscv/insn_trans/trans_rvi.c.inc
> @@ -404,6 +404,7 @@ static bool gen_load(DisasContext *ctx, arg_lb *a, MemOp 
> memop)
>  {
>      bool out;
>
> +    memop |= MO_TE;
>      if (ctx->cfg_ptr->ext_zama16b) {
>          memop |= MO_ATOM_WITHIN16;
>      }
> @@ -428,24 +429,24 @@ static bool trans_lb(DisasContext *ctx, arg_lb *a)
>
>  static bool trans_lh(DisasContext *ctx, arg_lh *a)
>  {
> -    return gen_load(ctx, a, MO_TE | MO_SW);
> +    return gen_load(ctx, a, MO_SW);
>  }
>
>  static bool trans_lw(DisasContext *ctx, arg_lw *a)
>  {
> -    return gen_load(ctx, a, MO_TE | MO_SL);
> +    return gen_load(ctx, a, MO_SL);
>  }
>
>  static bool trans_ld(DisasContext *ctx, arg_ld *a)
>  {
>      REQUIRE_64_OR_128BIT(ctx);
> -    return gen_load(ctx, a, MO_TE | MO_SQ);
> +    return gen_load(ctx, a, MO_SQ);
>  }
>
>  static bool trans_lq(DisasContext *ctx, arg_lq *a)
>  {
>      REQUIRE_128BIT(ctx);
> -    return gen_load(ctx, a, MO_TE | MO_UO);
> +    return gen_load(ctx, a, MO_UO);
>  }
>
>  static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
> @@ -455,19 +456,19 @@ static bool trans_lbu(DisasContext *ctx, arg_lbu *a)
>
>  static bool trans_lhu(DisasContext *ctx, arg_lhu *a)
>  {
> -    return gen_load(ctx, a, MO_TE | MO_UW);
> +    return gen_load(ctx, a, MO_UW);
>  }
>
>  static bool trans_lwu(DisasContext *ctx, arg_lwu *a)
>  {
>      REQUIRE_64_OR_128BIT(ctx);
> -    return gen_load(ctx, a, MO_TE | MO_UL);
> +    return gen_load(ctx, a, MO_UL);
>  }
>
>  static bool trans_ldu(DisasContext *ctx, arg_ldu *a)
>  {
>      REQUIRE_128BIT(ctx);
> -    return gen_load(ctx, a, MO_TE | MO_UQ);
> +    return gen_load(ctx, a, MO_UQ);
>  }
>
>  static bool gen_store_tl(DisasContext *ctx, arg_sb *a, MemOp memop)
> @@ -507,6 +508,7 @@ static bool gen_store_i128(DisasContext *ctx, arg_sb *a, 
> MemOp memop)
>
>  static bool gen_store(DisasContext *ctx, arg_sb *a, MemOp memop)
>  {
> +    memop |= MO_TE;
>      if (ctx->cfg_ptr->ext_zama16b) {
>          memop |= MO_ATOM_WITHIN16;
>      }
> @@ -525,24 +527,24 @@ static bool trans_sb(DisasContext *ctx, arg_sb *a)
>
>  static bool trans_sh(DisasContext *ctx, arg_sh *a)
>  {
> -    return gen_store(ctx, a, MO_TE | MO_SW);
> +    return gen_store(ctx, a, MO_SW);
>  }
>
>  static bool trans_sw(DisasContext *ctx, arg_sw *a)
>  {
> -    return gen_store(ctx, a, MO_TE | MO_SL);
> +    return gen_store(ctx, a, MO_SL);
>  }
>
>  static bool trans_sd(DisasContext *ctx, arg_sd *a)
>  {
>      REQUIRE_64_OR_128BIT(ctx);
> -    return gen_store(ctx, a, MO_TE | MO_UQ);
> +    return gen_store(ctx, a, MO_UQ);
>  }
>
>  static bool trans_sq(DisasContext *ctx, arg_sq *a)
>  {
>      REQUIRE_128BIT(ctx);
> -    return gen_store(ctx, a, MO_TE | MO_UO);
> +    return gen_store(ctx, a, MO_UO);
>  }
>
>  static bool trans_addd(DisasContext *ctx, arg_addd *a)
> diff --git a/target/riscv/insn_trans/trans_rvzce.c.inc 
> b/target/riscv/insn_trans/trans_rvzce.c.inc
> index d1301794324..c8dc102c8e3 100644
> --- a/target/riscv/insn_trans/trans_rvzce.c.inc
> +++ b/target/riscv/insn_trans/trans_rvzce.c.inc
> @@ -88,13 +88,13 @@ static bool trans_c_lbu(DisasContext *ctx, arg_c_lbu *a)
>  static bool trans_c_lhu(DisasContext *ctx, arg_c_lhu *a)
>  {
>      REQUIRE_ZCB(ctx);
> -    return gen_load(ctx, a, MO_TE | MO_UW);
> +    return gen_load(ctx, a, MO_UW);
>  }
>
>  static bool trans_c_lh(DisasContext *ctx, arg_c_lh *a)
>  {
>      REQUIRE_ZCB(ctx);
> -    return gen_load(ctx, a, MO_TE | MO_SW);
> +    return gen_load(ctx, a, MO_SW);
>  }
>
>  static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
> @@ -106,7 +106,7 @@ static bool trans_c_sb(DisasContext *ctx, arg_c_sb *a)
>  static bool trans_c_sh(DisasContext *ctx, arg_c_sh *a)
>  {
>      REQUIRE_ZCB(ctx);
> -    return gen_store(ctx, a, MO_TE | MO_UW);
> +    return gen_store(ctx, a, MO_UW);
>  }
>
>  #define X_S0    8
> --
> 2.51.0
>
>