Implementations can optionally write all bits of a mask production instruction, regardless of VL/SEW/LMUL configuration:
Furthermore, for mask-logical instructions and vmsbf.m, vmsif.m, vmsof.m mask-manipulation instructions, any element in the tail of the result can be written with the value the mask-producing operation would have calculated with vl=VLEN, SEW=8, and LMUL=8 (i.e., all bits of the mask register can be overwritten). Add mask_reg_full_update to cover this. Signed-off-by: Anton Blanchard <[email protected]> --- I just picked the next free bit for MASK_REG_FULL_UPDATE, I presume that is correct. target/riscv/cpu.c | 2 ++ target/riscv/cpu_cfg_fields.h.inc | 1 + target/riscv/insn_trans/trans_rvv.c.inc | 4 ++++ target/riscv/internals.h | 1 + target/riscv/translate.c | 2 ++ target/riscv/vector_internals.h | 5 +++++ 6 files changed, 15 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 2bd07a2f2b..671891f2a4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2688,6 +2688,8 @@ static const Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("rvv_ma_all_1s", RISCVCPU, cfg.rvv_ma_all_1s, false), DEFINE_PROP_BOOL("rvv_vl_half_avl", RISCVCPU, cfg.rvv_vl_half_avl, false), DEFINE_PROP_BOOL("rvv_vsetvl_x0_vill", RISCVCPU, cfg.rvv_vsetvl_x0_vill, false), + DEFINE_PROP_BOOL("rvv_mask_reg_full_update", RISCVCPU, + cfg.rvv_mask_reg_full_update, false), /* * write_misa() is marked as experimental for now so mark diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index 4c17f99dfd..abe27e985e 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -117,6 +117,7 @@ BOOL_FIELD(rvv_ta_all_1s) BOOL_FIELD(rvv_ma_all_1s) BOOL_FIELD(rvv_vl_half_avl) BOOL_FIELD(rvv_vsetvl_x0_vill) +BOOL_FIELD(rvv_mask_reg_full_update) /* Named features */ BOOL_FIELD(ext_svade) BOOL_FIELD(ext_zic64b) diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc index ef659f55fe..91e905caf7 100644 --- a/target/riscv/insn_trans/trans_rvv.c.inc +++ b/target/riscv/insn_trans/trans_rvv.c.inc @@ -3288,6 +3288,8 @@ static bool trans_##NAME(DisasContext *s, arg_r *a) \ data = FIELD_DP32(data, VDATA, LMUL, s->lmul); \ data = \ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ + data = FIELD_DP32(data, VDATA, MASK_REG_FULL_UPDATE, \ + s->cfg_mask_reg_full_update); \ tcg_gen_gvec_4_ptr(vreg_ofs(s, a->rd), vreg_ofs(s, 0), \ vreg_ofs(s, a->rs1), \ vreg_ofs(s, a->rs2), tcg_env, \ @@ -3387,6 +3389,8 @@ static bool trans_##NAME(DisasContext *s, arg_rmr *a) \ data = \ FIELD_DP32(data, VDATA, VTA_ALL_1S, s->cfg_vta_all_1s);\ data = FIELD_DP32(data, VDATA, VMA, s->vma); \ + data = FIELD_DP32(data, VDATA, MASK_REG_FULL_UPDATE, \ + s->cfg_mask_reg_full_update); \ tcg_gen_gvec_3_ptr(vreg_ofs(s, a->rd), \ vreg_ofs(s, 0), vreg_ofs(s, a->rs2), \ tcg_env, s->cfg_ptr->vlenb, \ diff --git a/target/riscv/internals.h b/target/riscv/internals.h index 172296f12e..a58c6caa69 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -70,6 +70,7 @@ FIELD(VDATA, VTA_ALL_1S, 5, 1) FIELD(VDATA, VMA, 6, 1) FIELD(VDATA, NF, 7, 4) FIELD(VDATA, WD, 7, 1) +FIELD(VDATA, MASK_REG_FULL_UPDATE, 11, 1) /* float point classify helpers */ target_ulong fclass_h(uint64_t frs1); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index e1f4dc5ffd..4f88e59182 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -101,6 +101,7 @@ typedef struct DisasContext { bool cfg_vta_all_1s; bool vstart_eq_zero; bool vl_eq_vlmax; + bool cfg_mask_reg_full_update; CPUState *cs; TCGv zero; /* actual address width */ @@ -1314,6 +1315,7 @@ static void riscv_tr_init_disas_context(DisasContextBase *dcbase, CPUState *cs) ctx->vta = FIELD_EX32(tb_flags, TB_FLAGS, VTA) && cpu->cfg.rvv_ta_all_1s; ctx->vma = FIELD_EX32(tb_flags, TB_FLAGS, VMA) && cpu->cfg.rvv_ma_all_1s; ctx->cfg_vta_all_1s = cpu->cfg.rvv_ta_all_1s; + ctx->cfg_mask_reg_full_update = cpu->cfg.rvv_mask_reg_full_update; ctx->vstart_eq_zero = FIELD_EX32(tb_flags, TB_FLAGS, VSTART_EQ_ZERO); ctx->vl_eq_vlmax = FIELD_EX32(tb_flags, TB_FLAGS, VL_EQ_VLMAX); ctx->misa_mxl_max = mcc->def->misa_mxl_max; diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h index 8eee7e5c31..383224341a 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -94,6 +94,11 @@ static inline uint32_t vext_vta_all_1s(uint32_t desc) return FIELD_EX32(simd_data(desc), VDATA, VTA_ALL_1S); } +static inline uint32_t vext_mask_reg_full_update(uint32_t desc) +{ + return FIELD_EX32(simd_data(desc), VDATA, MASK_REG_FULL_UPDATE); +} + /* * Earlier designs (pre-0.9) had a varying number of bits * per mask value (MLEN). In the 0.9 design, MLEN=1. -- 2.34.1
