Hi Tao,
On 20/1/26 02:02, Tao Tang wrote:
On 2026/1/20 01:22, Philippe Mathieu-Daudé wrote:
On 19/1/26 17:51, Tao Tang wrote:
Hi Philippe,
On 2026/1/20 00:38, Philippe Mathieu-Daudé wrote:
On 19/1/26 17:11, Tao Tang wrote:
Switch STE/CD bitfield definitions and accessors to the
'registerfields.h' REG/FIELD API.
FOLLOW-UP: Fix CTXPTR_HI/S2TTB_HI/TTB0_HI/TTB1_HI high bits width
(should be 24 bits, not 16).
Right, but ...
Signed-off-by: Tao Tang <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Eric Auger <[email protected]>
---
include/hw/arm/smmuv3-common.h | 169 ++++++++++++++++++++++
+----------
1 file changed, 120 insertions(+), 49 deletions(-)
-#define STE_VALID(x) extract32((x)->word[0], 0, 1)
+REG32(STE_0, 0)
+ FIELD(STE_0, VALID, 0, 1)
+ FIELD(STE_0, CONFIG, 1, 3)
+ FIELD(STE_0, S1FMT, 4, 2)
+ FIELD(STE_0, CTXPTR_LO, 6, 26)
+REG32(STE_1, 4)
+ FIELD(STE_1, CTXPTR_HI, 0, 16)
... not followed up?
Sorry, there's a typo here. What I was thinking at the time was
that I would submit a separate patch follow this series.
I squashed:
-- >8 --
diff --git a/include/hw/arm/smmuv3-common.h b/include/hw/arm/smmuv3-
common.h
index 6b48b5414dd..db30331441a 100644
--- a/include/hw/arm/smmuv3-common.h
+++ b/include/hw/arm/smmuv3-common.h
@@ -43,7 +43,7 @@ REG32(STE_0, 0)
FIELD(STE_0, S1FMT, 4, 2)
FIELD(STE_0, CTXPTR_LO, 6, 26)
REG32(STE_1, 4)
- FIELD(STE_1, CTXPTR_HI, 0, 16)
+ FIELD(STE_1, CTXPTR_HI, 0, 24)
FIELD(STE_1, S1CDMAX, 27, 5)
REG32(STE_2, 8)
FIELD(STE_2, S1STALLD, 27, 1)
(1/2) Stage this hunk [y,n,q,a,d,k,K,j,J,g,/,e,p,P,?]? y
@@ -66,7 +66,7 @@ REG32(STE_5, 20)
REG32(STE_6, 24)
FIELD(STE_6, S2TTB_LO, 4, 28)
REG32(STE_7, 28)
- FIELD(STE_7, S2TTB_HI, 0, 16)
+ FIELD(STE_7, S2TTB_HI, 0, 24)
---
Is that OK with you? Do TTB0_HI/TTB1_HI need update too?
Yes we should update TTB0_HI/TTB1_HI too. A total of four
modifications are needed here:
CTXPTR_HI
S2TTB_HI
TTB0_HI
TTB1_HI
I am just trying to help you getting your series merged. I know this is
v9 and you might be frustrated, but simply providing the correct 4
values would have helped both of us and save further exchanges.
In v8 Eric said to change 16 -> 24 for 4 fields and you confirmed:
https://lore.kernel.org/qemu-devel/[email protected]/
Looking at ARM IHI 0070G.b this is only valid for CTXPTR_HI, for the
rest only 20 bits remains, 4 are RES0 (SMMUv3.1).
It would have saved me some hours checking the spec if you had
provided the correct values beforehand. I'm going to squash the
following instead:
-- >8 --
diff --git a/include/hw/arm/smmuv3-common.h
b/include/hw/arm/smmuv3-common.h
index 6b48b5414dd..f0e1dd85715 100644
--- a/include/hw/arm/smmuv3-common.h
+++ b/include/hw/arm/smmuv3-common.h
@@ -45,3 +45,3 @@ REG32(STE_0, 0)
REG32(STE_1, 4)
- FIELD(STE_1, CTXPTR_HI, 0, 16)
+ FIELD(STE_1, CTXPTR_HI, 0, 24)
FIELD(STE_1, S1CDMAX, 27, 5)
@@ -68,3 +68,3 @@ REG32(STE_6, 24)
REG32(STE_7, 28)
- FIELD(STE_7, S2TTB_HI, 0, 16)
+ FIELD(STE_7, S2TTB_HI, 0, 20)
@@ -128,3 +128,3 @@ REG32(CD_2, 8)
REG32(CD_3, 12)
- FIELD(CD_3, TTB0_HI, 0, 19)
+ FIELD(CD_3, TTB0_HI, 0, 20)
REG32(CD_4, 16)
@@ -133,3 +133,3 @@ REG32(CD_4, 16)
REG32(CD_5, 20)
- FIELD(CD_5, TTB1_HI, 0, 19)
+ FIELD(CD_5, TTB1_HI, 0, 20)
---
If you disagree, please post a patch on top to correct.
Regards,
Phil.
