> On 25. Feb 2026, at 11:20, Djordje Todorovic
> <[email protected]> wrote:
>
> This series adds big-endian (BE) RISC-V target support to QEMU,
> covering both softmmu and linux-user emulation for riscv32be and
> riscv64be.
Hello,
There’s no Linux RISC-V big endian. Maybe the right thing to do is to not
support it unless we’re sure that it can get to Linux upstream (for the
linux-user mode)?
Thank you,
-Mohamed
>
> The RISC-V ISA supports big-endian operation via the mstatus SBE/MBE/UBE
> bits. While instructions are always little-endian, data accesses follow
> the configured endianness. This series implements the necessary QEMU
> infrastructure.
>
> Furthermore, MIPS announced cores with BE configuration:
> https://mips.com/products/hardware/i8500/
>
> Patches 01-03: Build system and config for new BE targets
> Patches 04-07: Core emulation fixes (instruction fetch, boot ROM, ELF
> loading, fw_dynamic endianness)
> Patches 08-11: Linux-user BE targets and vDSO handling
> Patch 12: Set SBE/MBE mstatus bits at CPU reset
> Patch 13: Fix PTE A/D atomic update endianness in page table walker
> Patch 14: Clean up instruction fetch to use MO_LE directly
> Patch 15: Fix virtio-mmio legacy device register endianness
> Patch 16: Add riscv32be and riscv64be to SysEmuTarget
>
> Djordje Todorovic (9):
> meson: Add BE RISCV targets
> config/targets: Add BE RISCV softmmu targets
> config/devices: Add BE riscv configs
> target/riscv: Ensure LE instruction fetching
> hw/riscv: Ensure bootrom has correct endianess
> hw/riscv: Ensure proper ELF endian expectation
> hw/riscv: Check endianness for fw_dynamic fields
> config/targets: Add RISC-V userspace targets
> arch/riscv: Set UBE bit on BE target
>
> djtodoro (7):
> config/targets: Add missing fields to BE linux-user targets
> linux-user/riscv: Disable vDSO for big-endian targets
> target/riscv: Set SBE and MBE bits at CPU reset for BE targets
> target/riscv: Fix PTE A/D atomic update endianness
> target/riscv: Use MO_LE for instruction fetch
> hw/virtio: Use DEVICE_LITTLE_ENDIAN for virtio-mmio legacy ops
> qapi: Add riscv32be and riscv64be to SysEmuTarget
>
> configs/devices/riscv32be-softmmu/default.mak | 15 +++++++
> configs/devices/riscv64be-softmmu/default.mak | 16 ++++++++
> configs/targets/riscv32be-linux-user.mak | 11 +++++
> configs/targets/riscv32be-softmmu.mak | 8 ++++
> configs/targets/riscv64be-linux-user.mak | 11 +++++
> configs/targets/riscv64be-softmmu.mak | 8 ++++
> hw/riscv/boot.c | 41 ++++++++++++++++---
> hw/virtio/virtio-mmio.c | 2 +-
> include/hw/riscv/boot.h | 5 +++
> linux-user/riscv/target_elf.h | 10 ++++-
> meson.build | 7 +++-
> qapi/machine.json | 3 +-
> target/riscv/cpu.c | 3 ++
> target/riscv/cpu_bits.h | 2 +
> target/riscv/cpu_helper.c | 9 ++--
> target/riscv/translate.c | 16 ++++----
> 16 files changed, 145 insertions(+), 22 deletions(-)
> create mode 100644 configs/devices/riscv32be-softmmu/default.mak
> create mode 100644 configs/devices/riscv64be-softmmu/default.mak
> create mode 100644 configs/targets/riscv32be-linux-user.mak
> create mode 100644 configs/targets/riscv32be-softmmu.mak
> create mode 100644 configs/targets/riscv64be-linux-user.mak
> create mode 100644 configs/targets/riscv64be-softmmu.mak
>
> --
> 2.34.1
>
