Re: [PATCH v2 07/16] hw/riscv: Check endianness for fw_dynamic fields

[Philippe Mathieu-Daudé]

On 27/2/26 00:32, Alistair Francis wrote:

On Wed, Feb 25, 2026 at 8:20 PM Djordje Todorovic
<djordje.todoro...@htecgroup.com> wrote:

For riscvbe target, the fields for OpenSBI's fw_payload
need to be in target endian.
---
  hw/riscv/boot.c         | 14 ++++++++++++++
  include/hw/riscv/boot.h |  5 +++++
  2 files changed, 19 insertions(+)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index 6dab521a6b..f13264a87f 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -396,19 +396,33 @@ void riscv_rom_copy_firmware_info(MachineState *machine,
      size_t dinfo_len;

      if (riscv_is_32bit(harts)) {
+#if TARGET_BIG_ENDIAN

This will need to be done without adding any TARGET_BIG_ENDIAN macros.
We don't want to have custom built binaries

Indeed. You should check the HART endianness.

An useful exercise is to consider a system with 2 HARTs running
in different endianness. QEMU should be able to run that setup.

Alistair