When the big-endian CPU property is enabled, set the MSTATUS_UBE
(User Big-Endian), MSTATUS_SBE (Supervisor Big-Endian), and
MSTATUS_MBE (Machine Big-Endian) bits during CPU reset.
This configures all privilege levels for big-endian data access,
matching the RISC-V privileged specification's endianness control
mechanism. Instructions remain little-endian regardless.
Also update the disassembler comment to clarify that
BFD_ENDIAN_LITTLE is correct because RISC-V instructions are
always little-endian per the ISA specification.
---
target/riscv/cpu.c | 10 +++++-----
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 305a8d73ad..4e5781ff04 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -717,6 +717,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType
type)
env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);
}
}
+ if (cpu->cfg.big_endian) {
+ env->mstatus |= MSTATUS_UBE | MSTATUS_SBE | MSTATUS_MBE;
+ }
env->mcause = 0;
env->miclaim = MIP_SGEIP;
env->pc = env->resetvec;
@@ -804,11 +807,8 @@ static void riscv_cpu_disas_set_info(const CPUState *s,
disassemble_info *info)
info->target_info = &cpu->cfg;
/*
- * A couple of bits in MSTATUS set the endianness:
- * - MSTATUS_UBE (User-mode),
- * - MSTATUS_SBE (Supervisor-mode),
- * - MSTATUS_MBE (Machine-mode)
- * but we don't implement that yet.
+ * RISC-V instructions are always little-endian, regardless of the
+ * data endianness configured via MSTATUS UBE/SBE/MBE bits.
*/
info->endian = BFD_ENDIAN_LITTLE;
--
2.34.1
