On 11/3/26 12:59, Djordje Todorovic wrote:
Add a "big-endian" boolean property to the RISC-V CPU configuration,
defaulting to false (little-endian). This property allows machine
models to configure individual HARTs for big-endian data operation.
The RISC-V ISA supports big-endian data accesses via the mstatus
SBE/MBE/UBE bits, while instructions remain always little-endian.
This property provides the configuration interface; subsequent
patches will connect it to the CPU state and translation logic.
---
include/qemu/target-info.h | 9 +++++++++
target-info-stub.c | 8 +++++++-
target/riscv/cpu.c | 6 ++++++
target/riscv/cpu_cfg_fields.h.inc | 1 +
4 files changed, 23 insertions(+), 1 deletion(-)
diff --git a/include/qemu/target-info.h b/include/qemu/target-info.h
index 23c997de54..1701cc1c9d 100644
--- a/include/qemu/target-info.h
+++ b/include/qemu/target-info.h
@@ -50,6 +50,15 @@ const char *target_cpu_type(void);
*/
bool target_big_endian(void);
+/**
+ * target_set_big_endian:
+ * @big_endian: the new endianness setting
+ *
+ * Set the target endianness at runtime. Used by bi-endian targets
+ * (e.g. RISC-V) where data endianness is a runtime CPU property.
+ */
+void target_set_big_endian(bool big_endian);
+
/**
* target_base_arm:
*
diff --git a/target-info-stub.c b/target-info-stub.c
index f5896a7262..b6532c419a 100644
--- a/target-info-stub.c
+++ b/target-info-stub.c
@@ -22,7 +22,7 @@ QEMU_BUILD_BUG_ON(offsetof(ArchCPU, env) != sizeof(CPUState));
QEMU_BUILD_BUG_ON(TARGET_PAGE_BITS < TARGET_PAGE_BITS_MIN);
#endif
-static const TargetInfo target_info_stub = {
+static TargetInfo target_info_stub = {
NAck. This structure must stay const. (this change isn't even
documented / justified).
What is the problem you are trying to resolve here?
.target_name = TARGET_NAME,
.target_arch = glue(SYS_EMU_TARGET_, TARGET_ARCH),
.long_bits = TARGET_LONG_BITS,
@@ -44,3 +44,9 @@ const TargetInfo *target_info(void)
{
return &target_info_stub;
}
+
+void target_set_big_endian(bool big_endian)
+{
+ target_info_stub.endianness = big_endian
+ ? ENDIAN_MODE_BIG : ENDIAN_MODE_LITTLE;
+}
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e56470a374..305a8d73ad 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -34,6 +34,7 @@
#include "system/device_tree.h"
#include "system/kvm.h"
#include "system/tcg.h"
+#include "qemu/target-info.h"
#include "kvm/kvm_riscv.h"
#include "tcg/tcg-cpu.h"
#include "tcg/tcg.h"
@@ -941,6 +942,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
return;
}
+ if (cpu->cfg.big_endian) {
+ target_set_big_endian(true);
+ }
+
riscv_cpu_register_gdb_regs_for_features(cs);
#ifndef CONFIG_USER_ONLY
@@ -2641,6 +2646,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[]
= {
static const Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
+ DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false),
{.name = "pmu-mask", .info = &prop_pmu_mask},
{.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */
diff --git a/target/riscv/cpu_cfg_fields.h.inc
b/target/riscv/cpu_cfg_fields.h.inc
index 70ec650abf..51436daabf 100644
--- a/target/riscv/cpu_cfg_fields.h.inc
+++ b/target/riscv/cpu_cfg_fields.h.inc
@@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop)
BOOL_FIELD(ext_xmipscmov)
BOOL_FIELD(ext_xmipslsp)
+BOOL_FIELD(big_endian)
BOOL_FIELD(mmu)
BOOL_FIELD(pmp)
BOOL_FIELD(debug)
