On 11/3/26 12:59, Djordje Todorovic wrote:
Add the RISC-V privileged ISA defined bit positions for the Supervisor
Big-Endian (SBE, bit 36) and Machine Big-Endian (MBE, bit 37) fields
in the mstatus register. These are used alongside the existing
MSTATUS_UBE (bit 6) to control data endianness at each privilege level.
The MSTATUS_UBE definition was already present, but SBE and MBE were
missing.
---
target/riscv/cpu_bits.h | 2 ++
1 file changed, 2 insertions(+)
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
