Thanks to Frédéric patch on 128-bit registers, we can now remove all legacy native endianness API uses of RISC-V.
Djordje: You should (re)base your "Add RISC-V big-endian target support" [*] series on this (after addressing the review comments) before posting your v4. [*] https://lore.kernel.org/qemu-devel/[email protected]/ Djordje Todorovic (1): target/riscv: Use MO_LE for instruction fetch Frédéric Pétrot (2): target/riscv: Make LQ and SQ use 128-bit ld/st target/riscv: Remove MTTCG check for x-rv128 CPU model Philippe Mathieu-Daudé (13): hw/riscv: Mark RISC-V specific peripherals as little-endian target/riscv: Use explicit little-endian LD/ST API target/riscv: Explode MO_TExx -> MO_TE | MO_xx (again) target/riscv: Conceal MO_ALIGN|MO_TE within load_acquire / store_release target/riscv: Factor tiny ldn() helper in gdbstub target/riscv: Simplify riscv_cpu_gdb_write_register() target/riscv: Expose mo_endian_env() target/riscv: Have gdbstub consider CPU endianness target/riscv: Replace MO_TE by mo_endian (MIPS extension) target/riscv: Replace MO_TE by mo_endian (Zilsd extension) target/riscv: Replace MO_TE by mo_endian (Zalasr extension) target/riscv: Replace MO_TE -> MO_LE configs/targets: Forbid RISC-V to use legacy native endianness APIs configs/targets/riscv32-linux-user.mak | 1 + configs/targets/riscv32-softmmu.mak | 1 + configs/targets/riscv64-bsd-user.mak | 1 + configs/targets/riscv64-linux-user.mak | 1 + configs/targets/riscv64-softmmu.mak | 1 + target/riscv/internals.h | 12 ++++++ hw/char/ibex_uart.c | 2 +- hw/char/shakti_uart.c | 2 +- hw/char/sifive_uart.c | 2 +- hw/misc/sifive_e_aon.c | 2 +- hw/misc/sifive_e_prci.c | 2 +- hw/misc/sifive_u_otp.c | 2 +- hw/misc/sifive_u_prci.c | 2 +- hw/riscv/riscv-iommu.c | 2 +- hw/sd/cadence_sdhci.c | 2 +- hw/timer/ibex_timer.c | 2 +- hw/timer/sifive_pwm.c | 2 +- target/riscv/cpu_helper.c | 4 +- target/riscv/gdbstub.c | 42 ++++++++------------ target/riscv/op_helper.c | 14 ------- target/riscv/tcg/tcg-cpu.c | 10 ----- target/riscv/translate.c | 10 ++--- target/riscv/insn_trans/trans_rvi.c.inc | 32 +++++++++++---- target/riscv/insn_trans/trans_rvzalasr.c.inc | 18 +++++---- target/riscv/insn_trans/trans_xmips.c.inc | 24 +++++++---- target/riscv/insn_trans/trans_zilsd.c.inc | 4 +- 26 files changed, 104 insertions(+), 93 deletions(-) -- 2.53.0
