Add a "big-endian" boolean property to the RISC-V CPU configuration, defaulting to false (little-endian). This property allows machine models to configure individual HARTs for big-endian data operation.
The RISC-V ISA supports big-endian data accesses via the mstatus SBE/MBE/UBE bits, while instructions remain always little-endian. This property provides the configuration interface; subsequent patches will connect it to the CPU state and translation logic. Signed-off-by: Djordje Todorovic <[email protected]> --- target/riscv/cpu.c | 1 + target/riscv/cpu_cfg_fields.h.inc | 1 + 2 files changed, 2 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index e56470a374..4537305dfe 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -2641,6 +2641,7 @@ RISCVCPUImpliedExtsRule *riscv_multi_ext_implied_rules[] = { static const Property riscv_cpu_properties[] = { DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true), + DEFINE_PROP_BOOL("big-endian", RISCVCPU, cfg.big_endian, false), {.name = "pmu-mask", .info = &prop_pmu_mask}, {.name = "pmu-num", .info = &prop_pmu_num}, /* Deprecated */ diff --git a/target/riscv/cpu_cfg_fields.h.inc b/target/riscv/cpu_cfg_fields.h.inc index 70ec650abf..51436daabf 100644 --- a/target/riscv/cpu_cfg_fields.h.inc +++ b/target/riscv/cpu_cfg_fields.h.inc @@ -154,6 +154,7 @@ BOOL_FIELD(ext_xmipscbop) BOOL_FIELD(ext_xmipscmov) BOOL_FIELD(ext_xmipslsp) +BOOL_FIELD(big_endian) BOOL_FIELD(mmu) BOOL_FIELD(pmp) BOOL_FIELD(debug) -- 2.34.1
