Add the RISC-V privileged ISA defined bit positions for the Supervisor Big-Endian (SBE, bit 36) and Machine Big-Endian (MBE, bit 37) fields in the mstatus register. These are used alongside the existing MSTATUS_UBE (bit 6) to control data endianness at each privilege level.
The MSTATUS_UBE definition was already present, but SBE and MBE were missing. Signed-off-by: Djordje Todorovic <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/cpu_bits.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index b62dd82fe7..c2a3ee4bf3 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -628,6 +628,8 @@ #define MSTATUS_TSR 0x00400000 /* since: priv-1.10 */ #define MSTATUS_SPELP 0x00800000 /* zicfilp */ #define MSTATUS_SDT 0x01000000 +#define MSTATUS_SBE 0x1000000000ULL +#define MSTATUS_MBE 0x2000000000ULL #define MSTATUS_MPELP 0x020000000000 /* zicfilp */ #define MSTATUS_GVA 0x4000000000ULL #define MSTATUS_MPV 0x8000000000ULL -- 2.34.1
