On 5/11/26 13:22, James Hilliard wrote:
+static bool trans_mtp(DisasContext *ctx, arg_r2 *a, unsigned int index)
+{
+ TCGv_i64 value = tcg_temp_new_i64();
+
+ /*
+ * Octeon3 two-source MTP forms load lane index from rs and lane index + 3
+ * from rt. Legacy one-source forms encode rt as $zero.
+ */
+ gen_load_gpr(value, a->rs);
+ octeon_store_p(index, value);
+ gen_load_gpr(value, a->rt);
+ octeon_store_p(index + 3, value);
+ if (index == 0) {
+ /*
+ * The hardware description and register-state table define P1 as zero;
+ * model P2/P4/P5 as zero for deterministic emulation.
+ */
+ TCGv_i64 zero = tcg_constant_i64(0);
+
+ octeon_store_p(1, zero);
+ octeon_store_p(2, zero);
+ octeon_store_p(4, zero);
+ octeon_store_p(5, zero);
Likewise, where does this come from?
The octeon2 manual for MTP* are quite simple, writing to just the one register.
r~
