On Tue, May 12, 2026 at 1:31 PM Daniel Henrique Barboza <[email protected]> wrote: > > Use isa_edata_arr[] to enable all feasible extensions. Filter > experimental and vendor extensions by checking if the riscv,isa or the > prop name starts with 'x'. > > Signed-off-by: Daniel Henrique Barboza <[email protected]>
Acked-by: Alistair Francis <[email protected]> Alistair > --- > target/riscv/tcg/tcg-cpu.c | 11 ++++++++--- > 1 file changed, 8 insertions(+), 3 deletions(-) > > diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c > index b7d59f40f2..eb48a76a6d 100644 > --- a/target/riscv/tcg/tcg-cpu.c > +++ b/target/riscv/tcg/tcg-cpu.c > @@ -1614,13 +1614,18 @@ static void riscv_init_max_cpu_extensions(Object *obj) > { > RISCVCPU *cpu = RISCV_CPU(obj); > CPURISCVState *env = &cpu->env; > - const RISCVCPUMultiExtConfig *prop; > + const RISCVIsaExtData *edata; > > /* Enable RVG and RVV that are disabled by default */ > riscv_cpu_set_misa_ext(env, env->misa_ext | RVB | RVG | RVV); > > - for (prop = riscv_cpu_extensions; prop && prop->name; prop++) { > - isa_ext_update_enabled(cpu, prop->offset, true); > + for (edata = isa_edata_arr; edata && edata->name; edata++) { > + if (edata->name[0] == 'x' > + || (edata->prop_name && edata->prop_name[0] == 'x')) { > + continue; > + } > + > + isa_ext_update_enabled(cpu, edata->ext_enable_offset, true); > } > > /* > -- > 2.43.0 > >
