Add a mips64/mips64el linux-user TCG smoke test for representative Octeon integer, comparison, population count, and multiplier instruction paths. Include hardware-backed regression coverage for VMM0 MPL1 zeroing and MTP0 P1 zeroing.
Run the test with -cpu Octeon68XX and share the source between the mips64 and mips64el target directories. Signed-off-by: James Hilliard <[email protected]> --- Changes v2 -> v3: - Split the smoke test out of the combined Octeon arithmetic and memory instruction patch. (requested by Richard Henderson) Changes v5 -> v6: - Add VMM0/MPL1 and MTP0/P1 reset checks for the CN71XX-defined reset-state behavior. --- tests/tcg/mips/user/isa/octeon/octeon-insns.c | 204 ++++++++++++++++++++++++++ tests/tcg/mips64/Makefile.target | 20 +++ tests/tcg/mips64el/Makefile.target | 8 + 3 files changed, 232 insertions(+) diff --git a/tests/tcg/mips/user/isa/octeon/octeon-insns.c b/tests/tcg/mips/user/isa/octeon/octeon-insns.c new file mode 100644 index 0000000000..9153e37e9e --- /dev/null +++ b/tests/tcg/mips/user/isa/octeon/octeon-insns.c @@ -0,0 +1,204 @@ +/* + * Test Octeon-specific user-mode instructions. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <assert.h> +#include <stdint.h> + +static uint64_t octeon_baddu(uint64_t rs, uint64_t rt) +{ + uint64_t rd; + + asm volatile( + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + ".word 0x71095028\n\t" /* baddu $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [rs] "r" (rs), [rt] "r" (rt) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_dmul(uint64_t rs, uint64_t rt) +{ + uint64_t rd; + + asm volatile( + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + ".word 0x71095003\n\t" /* dmul $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [rs] "r" (rs), [rt] "r" (rt) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_dpop(uint64_t rs) +{ + uint64_t rd; + + asm volatile( + "move $8, %[rs]\n\t" + ".word 0x7100502d\n\t" /* dpop $10, $8 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [rs] "r" (rs) + : "$8", "$10"); + + return rd; +} + +static uint64_t octeon_seq(uint64_t rs, uint64_t rt) +{ + uint64_t rd; + + asm volatile( + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + ".word 0x7109502a\n\t" /* seq $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [rs] "r" (rs), [rt] "r" (rt) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_sne(uint64_t rs, uint64_t rt) +{ + uint64_t rd; + + asm volatile( + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + ".word 0x7109502b\n\t" /* sne $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [rs] "r" (rs), [rt] "r" (rt) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_vmulu(uint64_t mpl0, uint64_t rs, uint64_t rt) +{ + uint64_t rd; + + asm volatile( + "move $8, %[mpl0]\n\t" + "move $9, $0\n\t" + ".word 0x71090008\n\t" /* mtm0 $8, $9 */ + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [mpl0] "r" (mpl0), [rs] "r" (rs), [rt] "r" (rt) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_vmm0(uint64_t mpl0, uint64_t p0, + uint64_t rs, uint64_t rt) +{ + uint64_t rd; + + asm volatile( + "move $8, %[mpl0]\n\t" + "move $9, $0\n\t" + ".word 0x71090008\n\t" /* mtm0 $8, $9 */ + "move $8, %[p0]\n\t" + "move $9, $0\n\t" + ".word 0x71090009\n\t" /* mtp0 $8, $9 */ + "move $8, %[rs]\n\t" + "move $9, %[rt]\n\t" + ".word 0x71095010\n\t" /* vmm0 $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [mpl0] "r" (mpl0), [p0] "r" (p0), + [rs] "r" (rs), [rt] "r" (rt) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_vmm0_zeroes_mpl1(void) +{ + uint64_t rd; + + asm volatile( + "move $8, %[mpl0]\n\t" + "move $9, $0\n\t" + ".word 0x71090008\n\t" /* mtm0 $8, $9 */ + "move $8, %[mpl1]\n\t" + "move $9, $0\n\t" + ".word 0x7109000c\n\t" /* mtm1 $8, $9 */ + "move $8, %[vmm0_rs]\n\t" + "move $9, $0\n\t" + ".word 0x71095010\n\t" /* vmm0 $10, $8, $9 */ + "move $8, %[vmulu_rs]\n\t" + "move $9, $0\n\t" + ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */ + "move $8, $0\n\t" + "move $9, $0\n\t" + ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [mpl0] "r" (1ULL), [mpl1] "r" (1ULL), + [vmm0_rs] "r" (2ULL), [vmulu_rs] "r" (1ULL) + : "$8", "$9", "$10"); + + return rd; +} + +static uint64_t octeon_mtp0_zeroes_p1(void) +{ + uint64_t rd; + + asm volatile( + "move $8, %[mpl0]\n\t" + "move $9, $0\n\t" + ".word 0x71090008\n\t" /* mtm0 $8, $9 */ + "move $8, %[p1]\n\t" + "move $9, $0\n\t" + ".word 0x7109000a\n\t" /* mtp1 $8, $9 */ + "move $8, $0\n\t" + "move $9, $0\n\t" + ".word 0x71090009\n\t" /* mtp0 $8, $9 */ + "move $8, $0\n\t" + "move $9, $0\n\t" + ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */ + "move $8, $0\n\t" + "move $9, $0\n\t" + ".word 0x7109500f\n\t" /* vmulu $10, $8, $9 */ + "move %[rd], $10\n\t" + : [rd] "=r" (rd) + : [mpl0] "r" (0ULL), [p1] "r" (1ULL) + : "$8", "$9", "$10"); + + return rd; +} + +int main(void) +{ + assert(octeon_baddu(0x123, 0x0f0) == 0x13); + assert(octeon_dmul(0x12345678, 0x10) == 0x123456780); + assert(octeon_dpop(0xf0f0f0f0f0f0f0f0ULL) == 32); + assert(octeon_seq(0xabc, 0xabc) == 1); + assert(octeon_seq(0xabc, 0xdef) == 0); + assert(octeon_sne(0xabc, 0xabc) == 0); + assert(octeon_sne(0xabc, 0xdef) == 1); + assert(octeon_vmulu(5, 7, 11) == 46); + assert(octeon_vmm0(5, 13, 7, 11) == 59); + assert(octeon_vmm0_zeroes_mpl1() == 0); + assert(octeon_mtp0_zeroes_p1() == 0); + + return 0; +} diff --git a/tests/tcg/mips64/Makefile.target b/tests/tcg/mips64/Makefile.target new file mode 100644 index 0000000000..042855844a --- /dev/null +++ b/tests/tcg/mips64/Makefile.target @@ -0,0 +1,20 @@ +# -*- Mode: makefile -*- +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# MIPS64 - included from tests/tcg/Makefile.target +# + +MIPS64_SRC=$(SRC_PATH)/tests/tcg/mips64 +MIPS_OCTEON_SRC=$(SRC_PATH)/tests/tcg/mips/user/isa/octeon + +# Set search path for all sources +VPATH += $(MIPS64_SRC) $(MIPS_OCTEON_SRC) + +MIPS64_TESTS=octeon-insns + +TESTS += $(MIPS64_TESTS) + +$(MIPS64_TESTS): CFLAGS+=-mabi=64 + +run-octeon-insns: QEMU_OPTS+=-cpu Octeon68XX diff --git a/tests/tcg/mips64el/Makefile.target b/tests/tcg/mips64el/Makefile.target new file mode 100644 index 0000000000..dbc5f8dc5f --- /dev/null +++ b/tests/tcg/mips64el/Makefile.target @@ -0,0 +1,8 @@ +# -*- Mode: makefile -*- +# +# SPDX-License-Identifier: GPL-2.0-or-later +# +# MIPS64 little-endian - included from tests/tcg/Makefile.target +# + +include $(SRC_PATH)/tests/tcg/mips64/Makefile.target -- 2.54.0
