Octeon68XX cores implement CP1. Advertise that in the CPU definition by setting Config1.FP, enabling the writable Status bits, and providing the FCR0/FCR31 defaults used by this CPU model.
This lets guests observe the expected floating-point feature bits and use CP1 with -cpu Octeon68XX. Signed-off-by: James Hilliard <[email protected]> Tested-by: Philippe Mathieu-Daudé <[email protected]> --- Changes v1 -> v2: - Move this CPU-model correction into a separate final patch. (suggested by Philippe Mathieu-Daudé) --- target/mips/cpu-defs.c.inc | 10 ++++++++-- 1 file changed, 8 insertions(+), 2 deletions(-) diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index faefab0473..cc1916232f 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -997,7 +997,8 @@ const mips_def_t mips_defs[] = .CP0_PRid = 0x000D9100, .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | (MMU_TYPE_R4000 << CP0C0_MT), - .CP0_Config1 = MIPS_CONFIG1 | (0x3F << CP0C1_MMU) | + .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | + (0x3F << CP0C1_MMU) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) | (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP), @@ -1011,7 +1012,12 @@ const mips_def_t mips_defs[] = .CP0_PageGrain = (1 << CP0PG_ELPA), .SYNCI_Step = 32, .CCRes = 2, - .CP0_Status_rw_bitmask = 0x12F8FFFF, + .CP0_Status_rw_bitmask = 0x36F8FFFF, + .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) | + (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) | + (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV), + .CP1_fcr31 = 0, + .CP1_fcr31_rw_bitmask = 0xFF83FFFF, .SEGBITS = 42, .PABITS = 49, .insn_flags = CPU_MIPS64R2 | INSN_OCTEON, -- 2.54.0
