Add explicit decodetree entries and translator bindings for the Octeon HSH shared-window selectors and SHA3 operation selectors. These paths need helper calls because HSH/SHA3 selectors alias the architectural hash register window and operation selectors have visible side effects.
Keep HSH/SHA3 decode separate from direct register transfers because the shared hash-window aliases require helper-mediated state updates. Signed-off-by: James Hilliard <[email protected]> --- target/mips/tcg/octeon.decode | 75 ++++++++++++++++++++++++++++++++++++++ target/mips/tcg/octeon_translate.c | 75 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 150 insertions(+) diff --git a/target/mips/tcg/octeon.decode b/target/mips/tcg/octeon.decode index fe9c97e380..f224cdc7a3 100644 --- a/target/mips/tcg/octeon.decode +++ b/target/mips/tcg/octeon.decode @@ -106,6 +106,7 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_HSH_IV1 010010 00001 rt:5 0000 0000 0100 1001 &cp2 CVM_MF_HSH_IV2 010010 00001 rt:5 0000 0000 0100 1010 &cp2 CVM_MF_HSH_IV3 010010 00001 rt:5 0000 0000 0100 1011 &cp2 + CVM_MF_SHA3_DAT24 010010 00001 rt:5 0000 0000 0101 0000 &cp2 CVM_MF_GFM_MUL_REFLECT0 010010 00001 rt:5 0000 0000 0101 1000 &cp2 CVM_MF_GFM_MUL_REFLECT1 010010 00001 rt:5 0000 0000 0101 1001 &cp2 CVM_MF_GFM_RESINP_REFLECT0 010010 00001 rt:5 0000 0000 0101 1010 &cp2 @@ -130,6 +131,30 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MF_CRC_IV 010010 00001 rt:5 0000 0010 0000 0001 &cp2 CVM_MF_CRC_LEN 010010 00001 rt:5 0000 0010 0000 0010 &cp2 CVM_MF_CRC_IV_REFLECT 010010 00001 rt:5 0000 0010 0000 0011 &cp2 + CVM_MF_HSH_DATW0 010010 00001 rt:5 0000 0010 0100 0000 &cp2 + CVM_MF_HSH_DATW1 010010 00001 rt:5 0000 0010 0100 0001 &cp2 + CVM_MF_HSH_DATW2 010010 00001 rt:5 0000 0010 0100 0010 &cp2 + CVM_MF_HSH_DATW3 010010 00001 rt:5 0000 0010 0100 0011 &cp2 + CVM_MF_HSH_DATW4 010010 00001 rt:5 0000 0010 0100 0100 &cp2 + CVM_MF_HSH_DATW5 010010 00001 rt:5 0000 0010 0100 0101 &cp2 + CVM_MF_HSH_DATW6 010010 00001 rt:5 0000 0010 0100 0110 &cp2 + CVM_MF_HSH_DATW7 010010 00001 rt:5 0000 0010 0100 0111 &cp2 + CVM_MF_HSH_DATW8 010010 00001 rt:5 0000 0010 0100 1000 &cp2 + CVM_MF_HSH_DATW9 010010 00001 rt:5 0000 0010 0100 1001 &cp2 + CVM_MF_HSH_DATW10 010010 00001 rt:5 0000 0010 0100 1010 &cp2 + CVM_MF_HSH_DATW11 010010 00001 rt:5 0000 0010 0100 1011 &cp2 + CVM_MF_HSH_DATW12 010010 00001 rt:5 0000 0010 0100 1100 &cp2 + CVM_MF_HSH_DATW13 010010 00001 rt:5 0000 0010 0100 1101 &cp2 + CVM_MF_HSH_DATW14 010010 00001 rt:5 0000 0010 0100 1110 &cp2 + CVM_MF_HSH_DATW15 010010 00001 rt:5 0000 0010 0100 1111 &cp2 + CVM_MF_HSH_IVW0 010010 00001 rt:5 0000 0010 0101 0000 &cp2 + CVM_MF_HSH_IVW1 010010 00001 rt:5 0000 0010 0101 0001 &cp2 + CVM_MF_HSH_IVW2 010010 00001 rt:5 0000 0010 0101 0010 &cp2 + CVM_MF_HSH_IVW3 010010 00001 rt:5 0000 0010 0101 0011 &cp2 + CVM_MF_HSH_IVW4 010010 00001 rt:5 0000 0010 0101 0100 &cp2 + CVM_MF_HSH_IVW5 010010 00001 rt:5 0000 0010 0101 0101 &cp2 + CVM_MF_HSH_IVW6 010010 00001 rt:5 0000 0010 0101 0110 &cp2 + CVM_MF_HSH_IVW7 010010 00001 rt:5 0000 0010 0101 0111 &cp2 CVM_MF_GFM_MUL0 010010 00001 rt:5 0000 0010 0101 1000 &cp2 CVM_MF_GFM_MUL1 010010 00001 rt:5 0000 0010 0101 1001 &cp2 CVM_MF_GFM_RESINP0 010010 00001 rt:5 0000 0010 0101 1010 &cp2 @@ -146,6 +171,9 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_HSH_IV1 010010 00101 rt:5 0000 0000 0100 1001 &cp2 CVM_MT_HSH_IV2 010010 00101 rt:5 0000 0000 0100 1010 &cp2 CVM_MT_HSH_IV3 010010 00101 rt:5 0000 0000 0100 1011 &cp2 + CVM_MT_SHA3_DAT24 010010 00101 rt:5 0000 0000 0101 0000 &cp2 + CVM_MT_SHA3_DAT15 010010 00101 rt:5 0000 0000 0101 0001 &cp2 + CVM_MT_HSH_STARTSHA_COMPAT 010010 00101 rt:5 0000 0000 0101 0111 &cp2 CVM_MT_GFM_MUL_REFLECT0 010010 00101 rt:5 0000 0000 0101 1000 &cp2 CVM_MT_GFM_MUL_REFLECT1 010010 00101 rt:5 0000 0000 0101 1001 &cp2 CVM_MT_GFM_XOR0_REFLECT 010010 00101 rt:5 0000 0000 0101 1100 &cp2 @@ -175,20 +203,67 @@ LDX 011111 ..... ..... ..... 01000 001010 @lx CVM_MT_CRC_WRITE_BYTE_REFLECT 010010 00101 rt:5 0000 0010 0001 0100 &cp2 CVM_MT_CRC_WRITE_HALF_REFLECT 010010 00101 rt:5 0000 0010 0001 0101 &cp2 CVM_MT_CRC_WRITE_WORD_REFLECT 010010 00101 rt:5 0000 0010 0001 0110 &cp2 + CVM_MT_HSH_DATW0 010010 00101 rt:5 0000 0010 0100 0000 &cp2 + CVM_MT_HSH_DATW1 010010 00101 rt:5 0000 0010 0100 0001 &cp2 + CVM_MT_HSH_DATW2 010010 00101 rt:5 0000 0010 0100 0010 &cp2 + CVM_MT_HSH_DATW3 010010 00101 rt:5 0000 0010 0100 0011 &cp2 + CVM_MT_HSH_DATW4 010010 00101 rt:5 0000 0010 0100 0100 &cp2 + CVM_MT_HSH_DATW5 010010 00101 rt:5 0000 0010 0100 0101 &cp2 + CVM_MT_HSH_DATW6 010010 00101 rt:5 0000 0010 0100 0110 &cp2 + CVM_MT_HSH_DATW7 010010 00101 rt:5 0000 0010 0100 0111 &cp2 + CVM_MT_HSH_DATW8 010010 00101 rt:5 0000 0010 0100 1000 &cp2 + CVM_MT_HSH_DATW9 010010 00101 rt:5 0000 0010 0100 1001 &cp2 + CVM_MT_HSH_DATW10 010010 00101 rt:5 0000 0010 0100 1010 &cp2 + CVM_MT_HSH_DATW11 010010 00101 rt:5 0000 0010 0100 1011 &cp2 + CVM_MT_HSH_DATW12 010010 00101 rt:5 0000 0010 0100 1100 &cp2 + CVM_MT_HSH_DATW13 010010 00101 rt:5 0000 0010 0100 1101 &cp2 + CVM_MT_HSH_DATW14 010010 00101 rt:5 0000 0010 0100 1110 &cp2 + CVM_MT_HSH_DATW15 010010 00101 rt:5 0000 0010 0100 1111 &cp2 + CVM_MT_HSH_IVW0 010010 00101 rt:5 0000 0010 0101 0000 &cp2 + CVM_MT_HSH_IVW1 010010 00101 rt:5 0000 0010 0101 0001 &cp2 + CVM_MT_HSH_IVW2 010010 00101 rt:5 0000 0010 0101 0010 &cp2 + CVM_MT_HSH_IVW3 010010 00101 rt:5 0000 0010 0101 0011 &cp2 + CVM_MT_HSH_IVW4 010010 00101 rt:5 0000 0010 0101 0100 &cp2 + CVM_MT_HSH_IVW5 010010 00101 rt:5 0000 0010 0101 0101 &cp2 + CVM_MT_HSH_IVW6 010010 00101 rt:5 0000 0010 0101 0110 &cp2 + CVM_MT_HSH_IVW7 010010 00101 rt:5 0000 0010 0101 0111 &cp2 CVM_MT_GFM_MUL0 010010 00101 rt:5 0000 0010 0101 1000 &cp2 CVM_MT_GFM_MUL1 010010 00101 rt:5 0000 0010 0101 1001 &cp2 CVM_MT_GFM_RESINP0 010010 00101 rt:5 0000 0010 0101 1010 &cp2 CVM_MT_GFM_RESINP1 010010 00101 rt:5 0000 0010 0101 1011 &cp2 CVM_MT_GFM_XOR0 010010 00101 rt:5 0000 0010 0101 1100 &cp2 CVM_MT_GFM_POLY 010010 00101 rt:5 0000 0010 0101 1110 &cp2 + CVM_MT_SHA3_XORDAT0 010010 00101 rt:5 0000 0010 1100 0000 &cp2 + CVM_MT_SHA3_XORDAT1 010010 00101 rt:5 0000 0010 1100 0001 &cp2 + CVM_MT_SHA3_XORDAT2 010010 00101 rt:5 0000 0010 1100 0010 &cp2 + CVM_MT_SHA3_XORDAT3 010010 00101 rt:5 0000 0010 1100 0011 &cp2 + CVM_MT_SHA3_XORDAT4 010010 00101 rt:5 0000 0010 1100 0100 &cp2 + CVM_MT_SHA3_XORDAT5 010010 00101 rt:5 0000 0010 1100 0101 &cp2 + CVM_MT_SHA3_XORDAT6 010010 00101 rt:5 0000 0010 1100 0110 &cp2 + CVM_MT_SHA3_XORDAT7 010010 00101 rt:5 0000 0010 1100 0111 &cp2 + CVM_MT_SHA3_XORDAT8 010010 00101 rt:5 0000 0010 1100 1000 &cp2 + CVM_MT_SHA3_XORDAT9 010010 00101 rt:5 0000 0010 1100 1001 &cp2 + CVM_MT_SHA3_XORDAT10 010010 00101 rt:5 0000 0010 1100 1010 &cp2 + CVM_MT_SHA3_XORDAT11 010010 00101 rt:5 0000 0010 1100 1011 &cp2 + CVM_MT_SHA3_XORDAT12 010010 00101 rt:5 0000 0010 1100 1100 &cp2 + CVM_MT_SHA3_XORDAT13 010010 00101 rt:5 0000 0010 1100 1101 &cp2 + CVM_MT_SHA3_XORDAT14 010010 00101 rt:5 0000 0010 1100 1110 &cp2 + CVM_MT_SHA3_XORDAT15 010010 00101 rt:5 0000 0010 1100 1111 &cp2 + CVM_MT_SHA3_XORDAT16 010010 00101 rt:5 0000 0010 1101 0000 &cp2 + CVM_MT_SHA3_XORDAT17 010010 00101 rt:5 0000 0010 1101 0001 &cp2 CVM_MT_CRC_WRITE_LEN 010010 00101 rt:5 0001 0010 0000 0010 &cp2 CVM_MT_CRC_WRITE_DWORD 010010 00101 rt:5 0001 0010 0000 0111 &cp2 CVM_MT_CRC_WRITE_VAR 010010 00101 rt:5 0001 0010 0000 1000 &cp2 CVM_MT_CRC_WRITE_DWORD_REFLECT 010010 00101 rt:5 0001 0010 0001 0111 &cp2 CVM_MT_CRC_WRITE_VAR_REFLECT 010010 00101 rt:5 0001 0010 0001 1000 &cp2 + CVM_MT_HSH_STARTMD5 010010 00101 rt:5 0100 0000 0100 0111 &cp2 + CVM_MT_HSH_STARTSHA256 010010 00101 rt:5 0100 0000 0100 1111 &cp2 + CVM_MT_SHA3_STARTOP 010010 00101 rt:5 0100 0000 0101 0010 &cp2 + CVM_MT_HSH_STARTSHA 010010 00101 rt:5 0100 0000 0101 0111 &cp2 CVM_MT_GFM_XORMUL1_REFLECT 010010 00101 rt:5 0100 0000 0101 1101 &cp2 CVM_MT_CRC_WRITE_POLYNOMIAL 010010 00101 rt:5 0100 0010 0000 0000 &cp2 CVM_MT_CRC_WRITE_POLYNOMIAL_REFLECT 010010 00101 rt:5 0100 0010 0001 0000 &cp2 + CVM_MT_HSH_STARTSHA512 010010 00101 rt:5 0100 0010 0100 1111 &cp2 CVM_MT_GFM_XORMUL1 010010 00101 rt:5 0100 0010 0101 1101 &cp2 ] } diff --git a/target/mips/tcg/octeon_translate.c b/target/mips/tcg/octeon_translate.c index ee69c7c652..c494eb9383 100644 --- a/target/mips/tcg/octeon_translate.c +++ b/target/mips/tcg/octeon_translate.c @@ -182,6 +182,31 @@ CP2_MF_I64(CVM_MF_GFM_RESINP1, gfm_resinp[1]); CP2_MF_U16(CVM_MF_GFM_POLY, gfm_poly); CP2_MF_HELPER(CVM_MF_CRC_IV_REFLECT, crc_iv_reflect); +CP2_MF_HELPER(CVM_MF_SHA3_DAT24, sha3_dat24); +CP2_MF_HELPER(CVM_MF_HSH_DATW0, hsh_dat0); +CP2_MF_HELPER(CVM_MF_HSH_DATW1, hsh_dat1); +CP2_MF_HELPER(CVM_MF_HSH_DATW2, hsh_dat2); +CP2_MF_HELPER(CVM_MF_HSH_DATW3, hsh_dat3); +CP2_MF_HELPER(CVM_MF_HSH_DATW4, hsh_dat4); +CP2_MF_HELPER(CVM_MF_HSH_DATW5, hsh_dat5); +CP2_MF_HELPER(CVM_MF_HSH_DATW6, hsh_dat6); +CP2_MF_HELPER(CVM_MF_HSH_DATW7, hsh_dat7); +CP2_MF_HELPER(CVM_MF_HSH_DATW8, hsh_dat8); +CP2_MF_HELPER(CVM_MF_HSH_DATW9, hsh_dat9); +CP2_MF_HELPER(CVM_MF_HSH_DATW10, hsh_dat10); +CP2_MF_HELPER(CVM_MF_HSH_DATW11, hsh_dat11); +CP2_MF_HELPER(CVM_MF_HSH_DATW12, hsh_dat12); +CP2_MF_HELPER(CVM_MF_HSH_DATW13, hsh_dat13); +CP2_MF_HELPER(CVM_MF_HSH_DATW14, hsh_dat14); +CP2_MF_HELPER(CVM_MF_HSH_DATW15, hsh_dat15); +CP2_MF_HELPER(CVM_MF_HSH_IVW0, hsh_iv0); +CP2_MF_HELPER(CVM_MF_HSH_IVW1, hsh_iv1); +CP2_MF_HELPER(CVM_MF_HSH_IVW2, hsh_iv2); +CP2_MF_HELPER(CVM_MF_HSH_IVW3, hsh_iv3); +CP2_MF_HELPER(CVM_MF_HSH_IVW4, hsh_iv4); +CP2_MF_HELPER(CVM_MF_HSH_IVW5, hsh_iv5); +CP2_MF_HELPER(CVM_MF_HSH_IVW6, hsh_iv6); +CP2_MF_HELPER(CVM_MF_HSH_IVW7, hsh_iv7); CP2_MT_I64(CVM_MT_HSH_DAT0, hsh_dat[0]); CP2_MT_I64(CVM_MT_HSH_DAT1, hsh_dat[1]); @@ -239,6 +264,56 @@ CP2_MT_HELPER(CVM_MT_CRC_WRITE_DWORD_REFLECT, crc_write_dword_reflect); CP2_MT_HELPER(CVM_MT_CRC_WRITE_VAR_REFLECT, crc_write_var_reflect); CP2_MT_HELPER(CVM_MT_GFM_XORMUL1_REFLECT, gfm_xormul1_reflect); CP2_MT_HELPER(CVM_MT_GFM_XORMUL1, gfm_xormul1); +CP2_MT_HELPER(CVM_MT_SHA3_DAT24, sha3_dat24); +CP2_MT_HELPER(CVM_MT_SHA3_DAT15, sha3_dat15); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT0, sha3_xordat0); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT1, sha3_xordat1); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT2, sha3_xordat2); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT3, sha3_xordat3); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT4, sha3_xordat4); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT5, sha3_xordat5); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT6, sha3_xordat6); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT7, sha3_xordat7); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT8, sha3_xordat8); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT9, sha3_xordat9); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT10, sha3_xordat10); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT11, sha3_xordat11); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT12, sha3_xordat12); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT13, sha3_xordat13); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT14, sha3_xordat14); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT15, sha3_xordat15); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT16, sha3_xordat16); +CP2_MT_HELPER(CVM_MT_SHA3_XORDAT17, sha3_xordat17); +CP2_MT_HELPER(CVM_MT_SHA3_STARTOP, sha3_startop); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA_COMPAT, hsh_startsha_compat); +CP2_MT_HELPER(CVM_MT_HSH_DATW0, hsh_dat0); +CP2_MT_HELPER(CVM_MT_HSH_DATW1, hsh_dat1); +CP2_MT_HELPER(CVM_MT_HSH_DATW2, hsh_dat2); +CP2_MT_HELPER(CVM_MT_HSH_DATW3, hsh_dat3); +CP2_MT_HELPER(CVM_MT_HSH_DATW4, hsh_dat4); +CP2_MT_HELPER(CVM_MT_HSH_DATW5, hsh_dat5); +CP2_MT_HELPER(CVM_MT_HSH_DATW6, hsh_dat6); +CP2_MT_HELPER(CVM_MT_HSH_DATW7, hsh_dat7); +CP2_MT_HELPER(CVM_MT_HSH_DATW8, hsh_dat8); +CP2_MT_HELPER(CVM_MT_HSH_DATW9, hsh_dat9); +CP2_MT_HELPER(CVM_MT_HSH_DATW10, hsh_dat10); +CP2_MT_HELPER(CVM_MT_HSH_DATW11, hsh_dat11); +CP2_MT_HELPER(CVM_MT_HSH_DATW12, hsh_dat12); +CP2_MT_HELPER(CVM_MT_HSH_DATW13, hsh_dat13); +CP2_MT_HELPER(CVM_MT_HSH_DATW14, hsh_dat14); +CP2_MT_HELPER(CVM_MT_HSH_DATW15, hsh_dat15); +CP2_MT_HELPER(CVM_MT_HSH_IVW0, hsh_iv0); +CP2_MT_HELPER(CVM_MT_HSH_IVW1, hsh_iv1); +CP2_MT_HELPER(CVM_MT_HSH_IVW2, hsh_iv2); +CP2_MT_HELPER(CVM_MT_HSH_IVW3, hsh_iv3); +CP2_MT_HELPER(CVM_MT_HSH_IVW4, hsh_iv4); +CP2_MT_HELPER(CVM_MT_HSH_IVW5, hsh_iv5); +CP2_MT_HELPER(CVM_MT_HSH_IVW6, hsh_iv6); +CP2_MT_HELPER(CVM_MT_HSH_IVW7, hsh_iv7); +CP2_MT_HELPER(CVM_MT_HSH_STARTMD5, hsh_startmd5); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA256, hsh_startsha256); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA, hsh_startsha); +CP2_MT_HELPER(CVM_MT_HSH_STARTSHA512, hsh_startsha512); static bool trans_BBIT(DisasContext *ctx, arg_BBIT *a) { -- 2.54.0
