Fix to 64 bits to hold all relevant values. Also update comment to reflect that irq_overflow_left stores the ns beyond INT64_MAX until the next overflow, this to account for the uint64_t/int64_t timer value difference between RISCV/QEMU.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Acked-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 9823d7d581..036709b9d6 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -223,8 +223,8 @@ typedef struct PMUCTRState { uint64_t mhpmcounter_val; /* Snapshot value of a counter */ uint64_t mhpmcounter_prev; - /* Value beyond UINT32_MAX/UINT64_MAX before overflow interrupt trigger */ - target_ulong irq_overflow_left; + /* Value beyond INT64_MAX before overflow interrupt trigger */ + uint64_t irq_overflow_left; } PMUCTRState; typedef struct PMUFixedCtrState { -- 2.52.0
