Fix to 64 bits to match size of instruction start words.
Signed-off-by: Anton Johansson <[email protected]>
Reviewed-by: Pierrick Bouvier <[email protected]>
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
Acked-by: Alistair Francis <[email protected]>
---
target/riscv/cpu.h | 2 +-
target/riscv/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index c93c8e3617..f4fcf65500 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -258,7 +258,7 @@ struct CPUArchState {
/* shadow stack register for zicfiss extension */
uint64_t ssp;
/* env place holder for extra word 2 during unwind */
- target_ulong excp_uw2;
+ uint64_t excp_uw2;
/* sw check code for sw check exception */
target_ulong sw_check_code;
#ifdef CONFIG_USER_ONLY
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 18a1e0ae99..9a0fd700d2 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -231,7 +231,7 @@ static void gen_check_nanbox_s(TCGv_i64 out, TCGv_i64 in)
tcg_gen_movcond_i64(TCG_COND_GEU, out, in, t_max, in, t_nan);
}
-static void decode_save_opc(DisasContext *ctx, target_ulong excp_uw2)
+static void decode_save_opc(DisasContext *ctx, uint64_t excp_uw2)
{
assert(!ctx->insn_start_updated);
ctx->insn_start_updated = true;
--
2.52.0
