The corresponding field CPUArchState::resetvec is uint64_t anyway, no need to use target_ulong.
Signed-off-by: Anton Johansson <[email protected]> Reviewed-by: Pierrick Bouvier <[email protected]> Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Reviewed-by: Alistair Francis <[email protected]> --- target/riscv/cpu.h | 2 +- target/riscv/cpu.c | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index a3ddae1e6a..de400437be 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -679,7 +679,7 @@ uint8_t riscv_cpu_get_fflags(CPURISCVState *env); void riscv_cpu_set_fflags(CPURISCVState *env, uint8_t); #ifndef CONFIG_USER_ONLY -void cpu_set_exception_base(int vp_index, target_ulong address); +void cpu_set_exception_base(int vp_index, uint64_t address); #endif FIELD(TB_FLAGS, MEM_IDX, 0, 3) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index daad317381..753f92307f 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -79,7 +79,7 @@ bool riscv_cpu_option_set(const char *optname) #ifndef CONFIG_USER_ONLY /* This is used in runtime only. */ -void cpu_set_exception_base(int vp_index, target_ulong address) +void cpu_set_exception_base(int vp_index, uint64_t address) { RISCVCPU *cpu; CPUState *cs = qemu_get_cpu(vp_index); -- 2.52.0
