We want to be able to reference ARMVectorType etc from common code, so move it out of cpu.h.
Reviewed-by: Philippe Mathieu-Daudé <[email protected]> Signed-off-by: Richard Henderson <[email protected]> --- target/arm/cpu.h | 38 +--------------------------------- target/arm/vector-type.h | 44 ++++++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+), 37 deletions(-) create mode 100644 target/arm/vector-type.h diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 9e637c1d80..9f5da3d863 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -35,6 +35,7 @@ #include "target/arm/cpu-sysregs.h" #include "target/arm/mmuidx.h" #include "hw/intc/arm_gicv5_types.h" +#include "target/arm/vector-type.h" #define EXCP_UDEF 1 /* undefined instruction */ #define EXCP_SWI 2 /* software interrupt */ @@ -140,43 +141,6 @@ typedef struct ARMGenericTimer { uint64_t ctl; /* Timer Control register */ } ARMGenericTimer; -/* Define a maximum sized vector register. - * For 32-bit, this is a 128-bit NEON/AdvSIMD register. - * For 64-bit, this is a 2048-bit SVE register. - * - * Note that the mapping between S, D, and Q views of the register bank - * differs between AArch64 and AArch32. - * In AArch32: - * Qn = regs[n].d[1]:regs[n].d[0] - * Dn = regs[n / 2].d[n & 1] - * Sn = regs[n / 4].d[n % 4 / 2], - * bits 31..0 for even n, and bits 63..32 for odd n - * (and regs[16] to regs[31] are inaccessible) - * In AArch64: - * Zn = regs[n].d[*] - * Qn = regs[n].d[1]:regs[n].d[0] - * Dn = regs[n].d[0] - * Sn = regs[n].d[0] bits 31..0 - * Hn = regs[n].d[0] bits 15..0 - * - * This corresponds to the architecturally defined mapping between - * the two execution states, and means we do not need to explicitly - * map these registers when changing states. - * - * Align the data for use with TCG host vector operations. - */ - -#define ARM_MAX_VQ 16 - -typedef struct ARMVectorReg { - uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); -} ARMVectorReg; - -/* In AArch32 mode, predicate registers do not exist at all. */ -typedef struct ARMPredicateReg { - uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); -} ARMPredicateReg; - /* In AArch32 mode, PAC keys do not exist at all. */ typedef struct ARMPACKey { uint64_t lo, hi; diff --git a/target/arm/vector-type.h b/target/arm/vector-type.h new file mode 100644 index 0000000000..d94c0d986e --- /dev/null +++ b/target/arm/vector-type.h @@ -0,0 +1,44 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef TARGET_ARM_VECTOR_TYPE_H +#define TARGET_ARM_VECTOR_TYPE_H + +/* + * Define a maximum sized vector register. + * For 32-bit, this is a 128-bit NEON/AdvSIMD register. + * For 64-bit, this is a 2048-bit SVE register. + * + * Note that the mapping between S, D, and Q views of the register bank + * differs between AArch64 and AArch32. + * In AArch32: + * Qn = regs[n].d[1]:regs[n].d[0] + * Dn = regs[n / 2].d[n & 1] + * Sn = regs[n / 4].d[n % 4 / 2], + * bits 31..0 for even n, and bits 63..32 for odd n + * (and regs[16] to regs[31] are inaccessible) + * In AArch64: + * Zn = regs[n].d[*] + * Qn = regs[n].d[1]:regs[n].d[0] + * Dn = regs[n].d[0] + * Sn = regs[n].d[0] bits 31..0 + * Hn = regs[n].d[0] bits 15..0 + * + * This corresponds to the architecturally defined mapping between + * the two execution states, and means we do not need to explicitly + * map these registers when changing states. + * + * Align the data for use with TCG host vector operations. + */ + +#define ARM_MAX_VQ 16 + +typedef struct ARMVectorReg { + uint64_t d[2 * ARM_MAX_VQ] QEMU_ALIGNED(16); +} ARMVectorReg; + +/* In AArch32 mode, predicate registers do not exist at all. */ +typedef struct ARMPredicateReg { + uint64_t p[DIV_ROUND_UP(2 * ARM_MAX_VQ, 8)] QEMU_ALIGNED(16); +} ARMPredicateReg; + +#endif -- 2.43.0
