Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/tcg/helper-fp8-defs.h | 3 ++
target/arm/tcg/fp8_helper.c | 55 ++++++++++++++++++++++++++++++++
target/arm/tcg/translate-a64.c | 3 ++
target/arm/tcg/a64.decode | 7 ++++
4 files changed, 68 insertions(+)
diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h
index 7aa8366d94..802a3b430e 100644
--- a/target/arm/tcg/helper-fp8-defs.h
+++ b/target/arm/tcg/helper-fp8-defs.h
@@ -26,3 +26,6 @@ DEF_HELPER_FLAGS_4(sme2_fcvtn_bs, TCG_CALL_NO_RWG, void, ptr,
ptr, env, i32)
DEF_HELPER_FLAGS_5(gvec_fmla_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
DEF_HELPER_FLAGS_5(gvec_fmla_idx_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,
env, i32)
+
+DEF_HELPER_FLAGS_5(gvec_fmla_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
+DEF_HELPER_FLAGS_5(gvec_fmla_idx_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr,
env, i32)
diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c
index d86d3d0bfb..a6e989f6b3 100644
--- a/target/arm/tcg/fp8_helper.c
+++ b/target/arm/tcg/fp8_helper.c
@@ -630,6 +630,16 @@ static float16 f8dotadd_h(uint64_t a, uint64_t b, int n,
float16 c,
return float16_round_pack_canonical(&p0, &ctx->stat);
}
+static float32 f8dotadd_s(uint64_t a, uint64_t b, int n, float32 c,
+ FP8MulContext *ctx)
+{
+ FloatParts64 p0 = f8dot(a, b, n, ctx);
+ FloatParts64 p1 = float32_unpack_canonical(c, &ctx->stat);
+
+ p0 = parts64_addsub(&p0, &p1, &ctx->stat, false);
+ return float32_round_pack_canonical(&p0, &ctx->stat);
+}
+
void HELPER(gvec_fmla_hb)(void *vd, void *vn, void *vm,
CPUARMState *env, uint32_t desc)
{
@@ -674,3 +684,48 @@ void HELPER(gvec_fmla_idx_hb)(void *vd, void *vn, void *vm,
clear_tail(vd, oprsz, simd_maxsz(desc));
}
+
+void HELPER(gvec_fmla_sb)(void *vd, void *vn, void *vm,
+ CPUARMState *env, uint32_t desc)
+{
+ FP8MulContext ctx = fp8_mul_start(env, -1);
+ size_t idx = extract32(desc, SIMD_DATA_SHIFT, 2);
+ size_t oprsz = simd_oprsz(desc);
+ size_t nelem = oprsz / 4;
+ uint8_t *n = vn;
+ uint8_t *m = vm;
+ float32 *d = vd;
+
+ for (size_t i = 0; i < nelem; i++) {
+ uint8_t e0 = n[H1(4 * i + idx)];
+ uint8_t e1 = m[H1(4 * i + idx)];
+
+ d[H4(i)] = f8dotadd_s(e0, e1, 1, d[H4(i)], &ctx);
+ }
+
+ clear_tail(vd, oprsz, simd_maxsz(desc));
+}
+
+void HELPER(gvec_fmla_idx_sb)(void *vd, void *vn, void *vm,
+ CPUARMState *env, uint32_t desc)
+{
+ FP8MulContext ctx = fp8_mul_start(env, -1);
+ size_t idx_n = extract32(desc, SIMD_DATA_SHIFT, 2);
+ size_t idx_m = extract32(desc, SIMD_DATA_SHIFT + 2, 4);
+ size_t oprsz = simd_oprsz(desc);
+ size_t nelem = oprsz / 4;
+ uint8_t *n = vn;
+ uint8_t *m = vm;
+ float32 *d = vd;
+ size_t i = 0;
+
+ do {
+ uint8_t e1 = m[4 * i + H1(idx_m)];
+ do {
+ uint8_t e0 = n[H1(4 * i + idx_n)];
+ d[H4(i)] = f8dotadd_s(e0, e1, 1, d[H4(i)], &ctx);
+ } while (++i % 4 != 0);
+ } while (i < nelem);
+
+ clear_tail(vd, oprsz, simd_maxsz(desc));
+}
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 1c1d4ad2f7..946c16d439 100644
--- a/target/arm/tcg/translate-a64.c
+++ b/target/arm/tcg/translate-a64.c
@@ -7400,6 +7400,9 @@ static bool do_fmla_fp8(DisasContext *s, arg_rxx *a,
TRANS_FEAT(FMLAL_hb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_hb)
TRANS_FEAT(FMLAL_hb_vi, aa64_f8fma, do_fmla_fp8, a,
gen_helper_gvec_fmla_idx_hb)
+TRANS_FEAT(FMLALL_sb_v, aa64_f8fma, do_fmla_fp8, a, gen_helper_gvec_fmla_sb)
+TRANS_FEAT(FMLALL_sb_vi, aa64_f8fma, do_fmla_fp8, a,
gen_helper_gvec_fmla_idx_sb)
+
static bool do_int3_vector_idx(DisasContext *s, arg_qrrx_e *a,
gen_helper_gvec_3 * const fns[2])
{
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index b89e83ce76..ef6d7dfeaa 100644
--- a/target/arm/tcg/a64.decode
+++ b/target/arm/tcg/a64.decode
@@ -1209,6 +1209,10 @@ FCVTN_bs 0.00 1110 000 ..... 11110 1 ..... .....
@qrrr_h
FMLAL_hb_v 0 idxn:1 00 1110 110 rm:5 11111 1 rn:5 rd:5 \
&rxx idxm=0
+%fmlall_idxn 30:1 22:1
+FMLALL_sb_v 0.00 1110 0.0 rm:5 110001 rn:5 rd:5 \
+ &rxx idxm=0 idxn=%fmlall_idxn
+
### Advanced SIMD scalar x indexed element
FMUL_si 0101 1111 00 .. .... 1001 . 0 ..... ..... @rrx_h
@@ -1330,6 +1334,9 @@ SQDMLSL_vi 0.00 1111 10 . ..... 0111 . 0 ..... .....
@qrrx_s
FMLAL_hb_vi 0 idxn:1 00 1111 11 ... rm:3 0000 . 0 rn:5 rd:5 \
&rxx idxm=%hlm4
+FMLALL_sb_vi 0 . 10 1111 0 . ... rm:3 1000 . 0 rn:5 rd:5 \
+ &rxx idxm=%hlm4 idxn=%fmlall_idxn
+
# Floating-point conditional select
FCSEL 0001 1110 .. 1 rm:5 cond:4 11 rn:5 rd:5 esz=%esz_hsd
--
2.43.0
