Introduce I2C controller support for the AST1040 SoC model. The I2C model type is selected from the SoC type name, allowing the AST1040 SoC to use the corresponding aspeed.i2c-ast1040 model.
The I2C controller is mapped at 0x74C0F000 and uses IRQs 64 - 77, with one IRQ assigned per I2C bus. The controller DRAM link is connected to SRAM1 (HyperRAM) for DMA support. Signed-off-by: Jamin Lin <[email protected]> --- hw/arm/aspeed_ast1040.c | 16 ++++++++++++++++ 1 file changed, 16 insertions(+) diff --git a/hw/arm/aspeed_ast1040.c b/hw/arm/aspeed_ast1040.c index 77211ce1f3..6d1cb9b102 100644 --- a/hw/arm/aspeed_ast1040.c +++ b/hw/arm/aspeed_ast1040.c @@ -117,6 +117,7 @@ static void aspeed_soc_ast1040_init(Object *obj) object_initialize_child(obj, "sgpio[*]", &s->sgpiom[i], "aspeed.sgpio-ast2700"); } + object_initialize_child(obj, "i2c", &s->i2c, TYPE_ASPEED_1040_I2C); object_initialize_child(obj, "pwm", &s->pwm, TYPE_UNIMPLEMENTED_DEVICE); object_initialize_child(obj, "espi", &s->espi, TYPE_UNIMPLEMENTED_DEVICE); @@ -233,6 +234,21 @@ static void aspeed_soc_ast1040_realize(DeviceState *dev_soc, Error **errp) aspeed_soc_ast1040_get_irq(s, ASPEED_DEV_SGPIOM0 + i)); } + /* I2C */ + object_property_set_link(OBJECT(&s->i2c), "dram", OBJECT(&s->sram[1]), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->i2c), errp)) { + return; + } + aspeed_mmio_map(s->memory, SYS_BUS_DEVICE(&s->i2c), 0, + sc->memmap[ASPEED_DEV_I2C]); + for (i = 0; i < ASPEED_I2C_GET_CLASS(&s->i2c)->num_busses; i++) { + qemu_irq irq = qdev_get_gpio_in(DEVICE(&a->armv7m), + sc->irqmap[ASPEED_DEV_I2C] + i); + /* The AST1040 I2C controller has one IRQ per bus. */ + sysbus_connect_irq(SYS_BUS_DEVICE(&s->i2c.busses[i]), 0, irq); + } + /* Unimplemented peripherals */ aspeed_mmio_map_unimplemented(s->memory, SYS_BUS_DEVICE(&s->pwm), "aspeed.pwm", -- 2.43.0
