Introducing Tenstorrent Atlantis! The Tenstorrent Atlantis platform is a collaboration between Tenstorrent and CoreLab Technology. It is based on the Atlantis SoC, which includes the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant RISC-V CPU. Thanks to Nick for sending the past few revs while I was on leave. v7: https://lore.kernel.org/qemu-riscv/[email protected]/ Changes since v7: Fixes for booting an external device tree. Will add a test for this once the device tree is reviewed. - Correct IMSIC memory layout to match hardware. Uses new patch 5. - Bring Zkr patch back in, required for opensbi to not trap on csr access - Address map corrections and ensure m-mode addresses are used for Linux devices - Use UART1 as the console to match hardware - Update /chosen so -append works - Update /memory node to match -m Others: - Fix duplicate .unimp setting in designware i2c - Avoid guest error warning at device reset time Chris Rauer (1): hw/i2c: Add DesignWare I2C Controller Joel Stanley (6): hw/riscv/virt: Move AIA initialisation to helper file hw/riscv/aia: Provide number of irq sources hw/riscv/aia: Configure stride for the M-mode IMSIC hw/riscv: Add Tenstorrent Atlantis machine hw/riscv/atlantis: Integrate i2c controllers hw/riscv/atlantis: Add some i2c peripherals Nicholas Piggin (5): hw/riscv/boot: Describe discontiguous memory in boot_info hw/riscv/boot: Account for discontiguous memory when loading firmware target/riscv: tt-ascalon: Enable Zkr extension hw/riscv/atlantis: Provide a simple halting payload tests/functional/riscv64: Add tt-atlantis tests MAINTAINERS | 19 + docs/system/riscv/tt_atlantis.rst | 41 + docs/system/target-riscv.rst | 1 + hw/riscv/aia.h | 26 + include/hw/i2c/designware_i2c.h | 56 ++ include/hw/riscv/boot.h | 12 +- include/hw/riscv/tt_atlantis.h | 64 ++ include/hw/riscv/virt.h | 2 +- hw/i2c/designware_i2c.c | 745 +++++++++++++++++++ hw/riscv/aia.c | 94 +++ hw/riscv/boot.c | 34 +- hw/riscv/microchip_pfsoc.c | 8 +- hw/riscv/opentitan.c | 6 +- hw/riscv/shakti_c.c | 6 +- hw/riscv/sifive_u.c | 6 +- hw/riscv/spike.c | 6 +- hw/riscv/tt_atlantis.c | 706 ++++++++++++++++++ hw/riscv/virt-acpi-build.c | 27 +- hw/riscv/virt.c | 97 +-- hw/riscv/xiangshan_kmh.c | 6 +- target/riscv/cpu.c | 1 + hw/i2c/Kconfig | 5 + hw/i2c/meson.build | 1 + hw/riscv/Kconfig | 13 + hw/riscv/meson.build | 3 +- tests/functional/riscv64/meson.build | 1 + tests/functional/riscv64/test_opensbi.py | 4 + tests/functional/riscv64/test_tt_atlantis.py | 57 ++ 28 files changed, 1940 insertions(+), 107 deletions(-) create mode 100644 docs/system/riscv/tt_atlantis.rst create mode 100644 hw/riscv/aia.h create mode 100644 include/hw/i2c/designware_i2c.h create mode 100644 include/hw/riscv/tt_atlantis.h create mode 100644 hw/i2c/designware_i2c.c create mode 100644 hw/riscv/aia.c create mode 100644 hw/riscv/tt_atlantis.c create mode 100755 tests/functional/riscv64/test_tt_atlantis.py -- 2.47.3
