On 4/6/26 05:03, Joel Stanley wrote:
On Wed, 3 Jun 2026 at 17:41, Philippe Mathieu-Daudé <[email protected]> wrote:
--- a/hw/riscv/aia.h
+++ b/hw/riscv/aia.h
@@ -14,6 +14,7 @@
uint32_t imsic_num_bits(uint32_t count);
DeviceState *riscv_create_aia(bool msimode, int aia_guests,
+ hwaddr m_imsic_stride,
hw/riscv/virt-acpi-build.c:74: uint64_t imsic_socket_addr, imsic_addr;
hw/riscv/virt.c:532: uint32_t imsic_max_hart_per_socket, imsic_addr,
imsic_size;
target/riscv/kvm/kvm-cpu.c:1829: uint64_t socket, base_hart,
hart_count, socket_imsic_base, imsic_addr;
Why choose hwaddr for a stride (region size)?
Brain fart.
Using uint64_t:
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
uint32_t would be more than sufficient too, do you agree?
Yes I was thinking the same, 32-bit is sufficient. But maybe
we should update the other cases for consistency (as a separate
patch)?
