On Tue, 9 Jun 2026 13:56:11 +0100, Jonathan Cameron <[email protected]> wrote:
Hi Jonathan, > +CC linux-cxl as that's where you are more likely to get feedback on > CXL aspects. > > For this one there is a more comprehensive solution that restricts this > to the cases that are valid (no interleaving going on). > https://lore.kernel.org/qemu-devel/[email protected]/#t > It is rather more complex as a result. > > For other cases we have always intentionally left it as not supporting > what you have here because we want the interleave to be correct and testable. > > As far as I'm concerned that series of Alireza's has been ready to merge for > a while. I've been a bit busy with other things so haven't been poking > for that though. Might be a week or two before I get back on top of things. > > Anyhow, please give Ali's series a go and see if that works for you. > There may well be other corners we haven't thought of! Thanks for pointing out Alireza's series. I'll test Alireza's series against the RISC-V virt machine with the same CXL + daxctl + virtio DMA workflow. If it resolves the issue, I'll drop this patch from v2 and just rebase patches 1-3. I'll report back once I've tested. Best, Pei
