This should point at the base of the Cortex-A9 MPCore private address space. If it doesn't we will confuse the Linux kernel as it probes the SCU registers and erroneously assumes the system is a buggy Aegis SOC and nerf the emission of SEV instructions, deadlocking any WFE's in the kernel (or QEMU smpboot code).
Signed-off-by: Alex Bennée <[email protected]> Suggested-by: Arnd Bergmann <[email protected]> --- hw/arm/npcm7xx.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index c2bbcd89dbc..c27f149c04a 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -492,7 +492,7 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) /* CPUs */ for (i = 0; i < nc->num_cpus; i++) { object_property_set_int(OBJECT(&s->cpu[i]), "reset-cbar", - NPCM7XX_GIC_CPU_IF_ADDR, &error_abort); + NPCM7XX_CPUP_BA, &error_abort); object_property_set_bool(OBJECT(&s->cpu[i]), "reset-hivecs", true, &error_abort); -- 2.47.3
