On 18/6/26 12:17, Peter Maydell wrote:
On Thu, 18 Jun 2026 at 11:07, Philippe Mathieu-Daudé
<[email protected]> wrote:
On 18/6/26 11:36, Alex Bennée wrote:
This should point at the base of the Cortex-A9 MPCore private address
space. If it doesn't we will confuse the Linux kernel as it probes the
SCU registers and erroneously assumes the system is a buggy Aegis SOC
and nerf the emission of SEV instructions, deadlocking any WFE's in
the kernel (or QEMU smpboot code).
I'm confused...
The Configuration Base Address Register holds the physical base
address of the memory-mapped GIC CPU interface registers.
Where did this quote come from? Note that the CBAR is an IMPDEF
sysreg, so its exact behaviour varies depending on the CPU model.
Oops I was looking at the A57 TRM, not A9:
https://developer.arm.com/documentation/ddi0488/h/system-control/aarch32-register-descriptions/configuration-base-address-register
The A9 TRM says:
https://developer.arm.com/documentation/ddi0388/i/system-control/register-descriptions/configuration-base-address-register?lang=en
In Cortex-A9 MPCore implementations, the base address is reset to
PERIPHBASE[31:13] so that software can determine the location of the
private memory region.
and then in the A9 MPCore TRM
https://developer.arm.com/documentation/ddi0407/g/Introduction/Private-Memory-Region
you can see that the private memory region has all the per-core
devices; the SCU happens to be the one at the start.
-- PMM
