On 18/6/26 12:12, Kuan-Jui Chiu wrote:
This patch adds a new model for Axiado AX3000 clock control which supports
to read ID and status
Signed-off-by: Kuan-Jui Chiu <[email protected]>
---
hw/misc/Kconfig | 3 ++
hw/misc/axiado_clk.c | 73 ++++++++++++++++++++++++++++++++++++
hw/misc/meson.build | 3 ++
include/hw/misc/axiado_clk.h | 26 +++++++++++++
4 files changed, 105 insertions(+)
create mode 100644 hw/misc/axiado_clk.c
create mode 100644 include/hw/misc/axiado_clk.h
diff --git a/hw/misc/axiado_clk.c b/hw/misc/axiado_clk.c
new file mode 100644
index 00000000000..6967a5995c5
--- /dev/null
+++ b/hw/misc/axiado_clk.c
@@ -0,0 +1,73 @@
+/*
+ * Axiado Clock Control
+ *
+ * Author: Kuan-Jui Chiu <[email protected]>
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "hw/misc/axiado_clk.h"
+
+#define CLKRST_CPU_PLL_POSTDIV_OFFSET 0x0C
+#define CLKRST_CPU_PLL_STS_OFFSET 0x14
+
+static uint64_t pll_read(void *opaque, hwaddr offset, unsigned size)
+{
+ switch (offset) {
+ case CLKRST_CPU_PLL_POSTDIV_OFFSET:
+ return 0x20891b;
+ case CLKRST_CPU_PLL_STS_OFFSET:
+ return 0x01;
+ default:
+ return 0x00;
+ }
+}
+
+static void pll_write(void *opaque, hwaddr offset, uint64_t val, unsigned size)
+{
Again, is this allowed? Could we log unexpected accesses?
+}
+
+static const MemoryRegionOps pll_ops = {
+ .read = pll_read,
+ .write = pll_write,
+ .endianness = DEVICE_LITTLE_ENDIAN,
+ .impl = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ },
+ .valid = {
+ .min_access_size = 4,
+ .max_access_size = 4,
+ }
+};
