Philippe Mathieu-Daudé 於 2026/6/18 下午 11:21 寫道:
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On 18/6/26 12:12, Kuan-Jui Chiu wrote:
Enable 8 Cadence GPIO controllers into Axiado AX3000 SoC
Signed-off-by: Kuan-Jui Chiu <[email protected]>
Reviewed-by: Peter Maydell <[email protected]>
---
hw/arm/Kconfig | 1 +
hw/arm/ax3000-soc.c | 30 ++++++++++++++++++++++++++++++
include/hw/arm/ax3000-soc.h | 21 +++++++++++++++++++++
3 files changed, 52 insertions(+)
static void ax3000_realize(DeviceState *dev, Error **errp)
@@ -183,6 +188,31 @@ static void ax3000_realize(DeviceState *dev,
Error **errp)
blk_by_legacy_dinfo((drive_get(IF_SD, 0, 0))),
&error_fatal);
qdev_realize_and_unref(card, s->sdhci0.sd_bus, &error_fatal);
+
+ /* GPIOs */
+ for (int i = 0; i < AX3000_NUM_GPIOS; i++) {
static const
I don't think we need static here because we don't need this struct for
entire lifetime
I can add const here to mark it as read-only and others
+ struct {
+ hwaddr addr;
+ unsigned int irq;
+ } gpio_table[] = {
+ { AX3000_GPIO0_BASE, AX3000_GPIO0_IRQ },
+ { AX3000_GPIO1_BASE, AX3000_GPIO1_IRQ },
+ { AX3000_GPIO2_BASE, AX3000_GPIO2_IRQ },
+ { AX3000_GPIO3_BASE, AX3000_GPIO3_IRQ },
+ { AX3000_GPIO4_BASE, AX3000_GPIO4_IRQ },
+ { AX3000_GPIO5_BASE, AX3000_GPIO5_IRQ },
+ { AX3000_GPIO6_BASE, AX3000_GPIO6_IRQ },
+ { AX3000_GPIO7_BASE, AX3000_GPIO7_IRQ }
+ };
+
+ if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio[i]), errp)) {
+ return;
+ }
+
+ sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio[i]), 0,
gpio_table[i].addr);
+ sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio[i]), 0,
+ qdev_get_gpio_in(gic_dev,
gpio_table[i].irq));
+ }
}
Reviewed-by: Philippe Mathieu-Daudé <[email protected]>
