On 19.06.26 07:44, Michael Tokarev wrote: > On 27.03.2026 17:34, Mathias Krause wrote: >> The control register bits haven't been updated in a few years, making >> them lack behind features QEMU ganied in these years. >> >> Update them to the current version of the SDM and sort the 32bit version >> to be in line with all the other definitions (descending order). >> >> This should remove confusion when debugging, for example, CET-enabled >> guests: >> >> - before the change: >> (gdb) info registers cr4 >> cr4 0x8000f0 [ PGE MCE PAE PSE ] >> >> - after the change: >> (gdb) info registers cr4 >> cr4 0x8000f0 [ CET PGE MCE PAE PSE ] >> >> Signed-off-by: Mathias Krause <[email protected]> > > This feels like a qemu-stable material, is it not?
Yes, I think so too (see [1]). That's why I tried to get it into 11.0 before its release but that didn't happen, unfortunately. :/ Would be nice if it could be included in a 11.x release, as that's the first with CET virtualization support. Thanks, Mathias [1] https://lore.kernel.org/qemu-devel/[email protected]/
