Reviewed-by: Caleb Schlossin <[email protected]>
On 6/17/26 4:50 AM, Saif Abrar wrote:
> From: Saif Abrar <[email protected]>
>
> Get the current link-status from PCIE macro.
> Extract link-speed and link-width from the link-status
> and set in the DLP training control (PCIE_DLP_TCR) register.
>
> Signed-off-by: Saif Abrar <[email protected]>
> Reviewed-by: Cédric Le Goater <[email protected]>
> Reviewed-by: Michael S. Tsirkin <[email protected]>
> Reviewed-by: Aditya Gupta <[email protected]>
> Reviewed-by: Jishnu Warrier <[email protected]>
> ---
> v5: Using be16_to_cpu as appropriate.
> v4: Variables declaration moved to the top of the method pnv_phb4_reg_read().
> v3: Updates for coding guidelines.
>
>
> hw/pci-host/pnv_phb4.c | 22 ++++++++++++++++++++--
> 1 file changed, 20 insertions(+), 2 deletions(-)
>
> diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c
> index 125f610790..e9d9323dba 100644
> --- a/hw/pci-host/pnv_phb4.c
> +++ b/hw/pci-host/pnv_phb4.c
> @@ -899,6 +899,7 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr
> off, unsigned size)
> PCIDevice *pdev = pci_find_device(pci->bus, 0, 0);
> uint32_t exp_base = get_exp_offset(pdev);
> uint64_t val;
> + uint32_t v, lnkstatus;
>
> if ((off & 0xfffc) == PHB_CONFIG_DATA) {
> return pnv_phb4_config_read(phb, off & 0x3, size);
> @@ -960,10 +961,27 @@ static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr
> off, unsigned size)
> val |= PHB_PCIE_SCR_PLW_X16; /* RO bit */
> break;
>
> - /* Link training always appears trained */
> case PHB_PCIE_DLP_TRAIN_CTL:
> - /* TODO: Do something sensible with speed ? */
> + /* Get the current link-status from PCIE */
> + lnkstatus = be16_to_cpu(pnv_phb4_rc_config_read(phb,
> + exp_base + PCI_EXP_LNKSTA, 4));
> +
> + /* Extract link-speed from the link-status */
> + v = lnkstatus & PCI_EXP_LNKSTA_CLS;
> +
> + /* Link training always appears trained */
> val |= PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT;
> +
> + /* Set the current link-speed at the LINK_SPEED position */
> + val = SETFIELD(PHB_PCIE_DLP_LINK_SPEED, val, v);
> +
> + /*
> + * Extract link-width from the link-status,
> + * after shifting the required bitfields.
> + */
> + v = (lnkstatus & PCI_EXP_LNKSTA_NLW) >> PCI_EXP_LNKSTA_NLW_SHIFT;
> + /* Set the current link-width at the LINK_WIDTH position */
> + val = SETFIELD(PHB_PCIE_DLP_LINK_WIDTH, val, v);
> return val;
>
> /*
