Reviewed-by: Caleb Schlossin <[email protected]>
On 6/17/26 4:50 AM, Saif Abrar wrote:
> From: Saif Abrar <[email protected]>
>
> New qtest testbench added for PHB[345].
> Testbench reads PHB Version register and asserts that
> bits[24:31] have value 0xA3, 0xA4 and 0xA5 respectively.
>
> Signed-off-by: Saif Abrar <[email protected]>
> Reviewed-by: Cédric Le Goater <[email protected]>
> Reviewed-by: Harsh Prateek Bora <[email protected]>
> Reviewed-by: Aditya Gupta <[email protected]>
> Reviewed-by: Jishnu Warrier <[email protected]>
> ---
> v5:
> - Rename qtest file and all methods to phb5.
> - New file for common defitions "pnv-qtest-common.h"
> v3: Updates for coding guidelines.
> v2: Added version check for PHB3 and PHB4 also.
>
>
> tests/qtest/meson.build | 1 +
> tests/qtest/pnv-host-i2c-test.c | 13 +----
> tests/qtest/pnv-phb-test.c | 100 ++++++++++++++++++++++++++++++++
> tests/qtest/pnv-qtest-common.h | 24 ++++++++
> tests/qtest/pnv-xive2-common.h | 7 +--
> 5 files changed, 127 insertions(+), 18 deletions(-)
> create mode 100644 tests/qtest/pnv-phb-test.c
> create mode 100644 tests/qtest/pnv-qtest-common.h
>
> diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build
> index 2ae720156f..d3fc532dcd 100644
> --- a/tests/qtest/meson.build
> +++ b/tests/qtest/meson.build
> @@ -186,6 +186,7 @@ qtests_ppc64 = \
> (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-xive2-test'] : []) +
> \
> (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-spi-seeprom-test'] :
> []) + \
> (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-host-i2c-test'] :
> []) + \
> + (config_all_devices.has_key('CONFIG_POWERNV') ? ['pnv-phb-test'] : []) +
> \
> (config_all_devices.has_key('CONFIG_PSERIES') ? ['numa-test'] : []) +
> \
> (config_all_devices.has_key('CONFIG_PSERIES') ? ['rtas-test'] : []) +
> \
> (slirp.found() ? ['pxe-test'] : []) + \
> diff --git a/tests/qtest/pnv-host-i2c-test.c b/tests/qtest/pnv-host-i2c-test.c
> index 51e613ebdc..5867416b26 100644
> --- a/tests/qtest/pnv-host-i2c-test.c
> +++ b/tests/qtest/pnv-host-i2c-test.c
> @@ -11,18 +11,7 @@
> #include "hw/gpio/pca9554_regs.h"
> #include "hw/gpio/pca9552_regs.h"
> #include "pnv-xscom.h"
> -
> -#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
> -#define PPC_BIT32(bit) (0x80000000 >> (bit))
> -#define PPC_BIT8(bit) (0x80 >> (bit))
> -#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> -#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
> - PPC_BIT32(bs))
> -
> -#define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
> -#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> -#define SETFIELD(m, v, val) \
> - (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
> +#include "pnv-qtest-common.h"
>
> #define PNV10_XSCOM_I2CM_BASE 0xa0000
> #define PNV10_XSCOM_I2CM_SIZE 0x1000
> diff --git a/tests/qtest/pnv-phb-test.c b/tests/qtest/pnv-phb-test.c
> new file mode 100644
> index 0000000000..2eda521249
> --- /dev/null
> +++ b/tests/qtest/pnv-phb-test.c
> @@ -0,0 +1,100 @@
> +/*
> + * QTest testcase for PowerNV PHB
> + *
> + * Copyright (c) 2026, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + *
> + */
> +
> +#include "qemu/osdep.h"
> +#include "libqtest.h"
> +#include "hw/pci-host/pnv_phb4_regs.h"
> +#include "pnv-xscom.h"
> +#include "pnv-qtest-common.h"
> +
> +#define PHB3_PBCQ_SPCI_ASB_ADDR 0x0
> +#define PHB3_PBCQ_SPCI_ASB_DATA 0x2
> +
> +/* Index of PNV_CHIP_POWER10 in pnv_chips[] within "pnv-xscom.h" */
> +#define PHB4_XSCOM 0x40084800ull
> +
> +/* SCOM to PCBA address conversion */
> +#define SCOM_TO_PCBA(scom, addr) (((scom) >> 3) + (addr))
> +
> +/*
> + * Indirect XSCOM read::
> + * - Write 'Indirect Address Register' with register-offset to read.
> + * - Read 'Indirect Data Register' to get the value.
> + */
> +static uint64_t pnv_phb_xscom_read(QTestState *qts, const PnvChip *chip,
> + uint64_t scom, uint32_t indirect_addr, uint32_t indirect_data,
> + uint64_t reg)
> +{
> + qtest_writeq(qts, pnv_xscom_addr(chip, SCOM_TO_PCBA(scom,
> indirect_addr)),
> + reg);
> + return qtest_readq(qts, pnv_xscom_addr(chip, SCOM_TO_PCBA(scom,
> +
> indirect_data)));
> +}
> +
> +/* Assert that 'PHB - Version Register' bits[24:31] are as expected */
> +static void phb_version_test(const void *data)
> +{
> + const PnvChip *chip = (PnvChip *)data;
> + QTestState *qts;
> + const char *machine = "powernv8";
> + uint64_t phb_xscom = 0x4809e000;
> + uint64_t reg_phb_version = PHB_VERSION;
> + uint32_t indirect_addr = PHB3_PBCQ_SPCI_ASB_ADDR;
> + uint32_t indirect_data = PHB3_PBCQ_SPCI_ASB_DATA;
> + uint32_t expected_ver = 0xA3;
> + uint64_t ver;
> +
> + if (chip->chip_type == PNV_CHIP_POWER9) {
> + machine = "powernv9";
> + phb_xscom = 0x68084800;
> + indirect_addr = PHB_SCOM_HV_IND_ADDR;
> + indirect_data = PHB_SCOM_HV_IND_DATA;
> + reg_phb_version |= PPC_BIT(0);
> + expected_ver = 0xA4;
> + } else if (chip->chip_type == PNV_CHIP_POWER10) {
> + machine = "powernv10";
> + phb_xscom = PHB4_XSCOM;
> + indirect_addr = PHB_SCOM_HV_IND_ADDR;
> + indirect_data = PHB_SCOM_HV_IND_DATA;
> + reg_phb_version |= PPC_BIT(0);
> + expected_ver = 0xA5;
> + }
> +
> + qts = qtest_initf("-M %s -accel tcg -cpu %s", machine, chip->cpu_model);
> +
> + ver = pnv_phb_xscom_read(qts, chip, phb_xscom,
> + indirect_addr, indirect_data,
> reg_phb_version);
> +
> + /* PHB Version register bits [24:31] */
> + ver = (ver & PPC_BITMASK(24, 31)) >> (63 - 31);
> + g_assert_cmpuint(ver, ==, expected_ver);
> +
> + qtest_quit(qts);
> +}
> +
> +/* Verify versions of all supported PHB's */
> +static void add_phbX_version_test(void)
> +{
> + for (int i = 0; i < ARRAY_SIZE(pnv_chips); i++) {
> + char *tname = g_strdup_printf("pnv-phb/%s",
> + pnv_chips[i].cpu_model);
> + qtest_add_data_func(tname, &pnv_chips[i], phb_version_test);
> + g_free(tname);
> + }
> +}
> +
> +int main(int argc, char **argv)
> +{
> + g_test_init(&argc, &argv, NULL);
> +
> + /* PHB[345] tests */
> + add_phbX_version_test();
> +
> + return g_test_run();
> +}
> diff --git a/tests/qtest/pnv-qtest-common.h b/tests/qtest/pnv-qtest-common.h
> new file mode 100644
> index 0000000000..c2d1bae7bb
> --- /dev/null
> +++ b/tests/qtest/pnv-qtest-common.h
> @@ -0,0 +1,24 @@
> +/*
> + * PNV QTest common definitions
> + *
> + * Copyright (c) 2026, IBM Corporation.
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef TEST_PNV_QTEST_COMMON_H
> +#define TEST_PNV_QTEST_COMMON_H
> +
> +#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
> +#define PPC_BIT32(bit) (0x80000000 >> (bit))
> +#define PPC_BIT8(bit) (0x80 >> (bit))
> +#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> +#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
> + PPC_BIT32(bs))
> +
> +#define MASK_TO_LSH(m) (__builtin_ffsll(m) - 1)
> +#define GETFIELD(m, v) (((v) & (m)) >> MASK_TO_LSH(m))
> +#define SETFIELD(m, v, val) \
> + (((v) & ~(m)) | ((((typeof(v))(val)) << MASK_TO_LSH(m)) & (m)))
> +
> +#endif
> diff --git a/tests/qtest/pnv-xive2-common.h b/tests/qtest/pnv-xive2-common.h
> index 3b84227424..4b823a57e2 100644
> --- a/tests/qtest/pnv-xive2-common.h
> +++ b/tests/qtest/pnv-xive2-common.h
> @@ -9,12 +9,7 @@
> #ifndef TEST_PNV_XIVE2_COMMON_H
> #define TEST_PNV_XIVE2_COMMON_H
>
> -#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
> -#define PPC_BIT32(bit) (0x80000000 >> (bit))
> -#define PPC_BIT8(bit) (0x80 >> (bit))
> -#define PPC_BITMASK(bs, be) ((PPC_BIT(bs) - PPC_BIT(be)) | PPC_BIT(bs))
> -#define PPC_BITMASK32(bs, be) ((PPC_BIT32(bs) - PPC_BIT32(be)) | \
> - PPC_BIT32(bs))
> +#include "pnv-qtest-common.h"
> #include "hw/intc/pnv_xive2_regs.h"
> #include "hw/ppc/xive_regs.h"
> #include "hw/ppc/xive2_regs.h"
