Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/cpu-features.h | 5 +++++
target/arm/tcg/helper-sme-defs.h | 1 +
target/arm/tcg/sme_helper.c | 6 ++++++
target/arm/tcg/translate-sme.c | 2 ++
target/arm/tcg/sme.decode | 1 +
5 files changed, 15 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index 4190398a1d..d3bf0746cb 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1842,6 +1842,11 @@ static inline bool
isar_feature_aa64_sme_mop4_i16i64(const ARMISARegisters *id)
return isar_feature_aa64_sme_mop4(id) && isar_feature_aa64_sme_i16i64(id);
}
+static inline bool isar_feature_aa64_sme_tmop_b16b16(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_b16b16(id);
+}
+
static inline bool isar_feature_aa64_sme_tmop_f16f16(const ARMISARegisters *id)
{
return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f16f16(id);
diff --git a/target/arm/tcg/helper-sme-defs.h b/target/arm/tcg/helper-sme-defs.h
index 84707e6c71..224de45294 100644
--- a/target/arm/tcg/helper-sme-defs.h
+++ b/target/arm/tcg/helper-sme-defs.h
@@ -405,5 +405,6 @@ DEF_HELPER_FLAGS_4(sme_usmop4s_sb, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sme_usmop4a_dh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
DEF_HELPER_FLAGS_4(sme_usmop4s_dh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32)
+DEF_HELPER_FLAGS_6(sme_bftmopa_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
fpst, i32)
DEF_HELPER_FLAGS_6(sme_ftmopa_hh, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
fpst, i32)
DEF_HELPER_FLAGS_6(sme_ftmopa_ss, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
fpst, i32)
diff --git a/target/arm/tcg/sme_helper.c b/target/arm/tcg/sme_helper.c
index 49fd3d07e4..e57c56d5f2 100644
--- a/target/arm/tcg/sme_helper.c
+++ b/target/arm/tcg/sme_helper.c
@@ -2831,6 +2831,12 @@ void HELPER(sme_bfmop4a_hh)(void *vza, void *vzn, void
*vzm,
sme_mop4(vza, vzn, vzm, fpst, desc, sizeof(bfloat16), inner_bfmop4a_hh);
}
+void HELPER(sme_bftmopa_hh)(void *vza, void *vzn, void *vzm, void *vzk,
+ float_status *fpst, uint32_t desc)
+{
+ sme_tmop(vza, vzn, vzm, vzk, fpst, desc, MO_16, inner_bfmop4a_hh);
+}
+
static void inner_bfmop4s_hh(void *vd, void *vn, void *vm, void *vinfo)
{
bfloat16 *d = vd, *n = vn, *m = vm;
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 6cb9628e75..7d21ebabc3 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -2156,6 +2156,8 @@ static bool do_tmop_fp(DisasContext *s, arg_tmop *a,
MemOp esz,
return true;
}
+TRANS_FEAT(BFTMOPA_hh, aa64_sme_tmop_b16b16, do_tmop_fp,
+ a, MO_16, FPST_ZA, gen_helper_sme_bftmopa_hh)
TRANS_FEAT(FTMOPA_hh, aa64_sme_tmop_f16f16, do_tmop_fp,
a, MO_16, FPST_ZA_F16, gen_helper_sme_ftmopa_hh)
TRANS_FEAT(FTMOPA_ss, aa64_sme_tmop, do_tmop_fp,
diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode
index 16ed3ca391..f0f9b3f61d 100644
--- a/target/arm/tcg/sme.decode
+++ b/target/arm/tcg/sme.decode
@@ -1142,5 +1142,6 @@ USMOP4_dh 1010 0001 110. ...0 0000 00.. ..0. 1...
@mop4_o3
@tmop_o2 .... .... ... zm:5 ... ... .... idx:2 .. zad:2 \
&tmop zn=%zn_ax2 zk=%tmop_zk
+BFTMOPA_hh 1000 0001 011 ..... 000 ... .... .. 100 . @tmop_o1
FTMOPA_hh 1000 0001 010 ..... 000 ... .... .. 100 . @tmop_o1
FTMOPA_ss 1000 0000 010 ..... 000 ... .... .. 00 .. @tmop_o2
--
2.43.0
