Signed-off-by: Richard Henderson <[email protected]>
---
target/arm/cpu-features.h | 5 ++++
target/arm/tcg/helper-fp8-defs.h | 2 ++
target/arm/tcg/fp8_helper.c | 43 ++++++++++++++++++++++++++++++++
target/arm/tcg/translate-sme.c | 12 +++++++++
target/arm/tcg/sme.decode | 2 ++
5 files changed, 64 insertions(+)
diff --git a/target/arm/cpu-features.h b/target/arm/cpu-features.h
index d3bf0746cb..1ab6c90b8c 100644
--- a/target/arm/cpu-features.h
+++ b/target/arm/cpu-features.h
@@ -1852,6 +1852,11 @@ static inline bool
isar_feature_aa64_sme_tmop_f16f16(const ARMISARegisters *id)
return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f16f16(id);
}
+static inline bool isar_feature_aa64_sme_tmop_f8f16(const ARMISARegisters *id)
+{
+ return isar_feature_aa64_sme_tmop(id) && isar_feature_aa64_sme_f8f16(id);
+}
+
/*
* Feature tests for "does this exist in either 32-bit or 64-bit?"
*/
diff --git a/target/arm/tcg/helper-fp8-defs.h b/target/arm/tcg/helper-fp8-defs.h
index dedbd8541c..13be62aa15 100644
--- a/target/arm/tcg/helper-fp8-defs.h
+++ b/target/arm/tcg/helper-fp8-defs.h
@@ -47,3 +47,5 @@ DEF_HELPER_FLAGS_5(sme_fvdot_idx_hb, TCG_CALL_NO_RWG, void,
ptr, ptr, ptr, env,
DEF_HELPER_FLAGS_5(sme_fmop4a_sb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
DEF_HELPER_FLAGS_5(sme_fmop4a_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, env,
i32)
+
+DEF_HELPER_FLAGS_6(sme_ftmopa_hb, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr,
env, i32)
diff --git a/target/arm/tcg/fp8_helper.c b/target/arm/tcg/fp8_helper.c
index 4b046f5f26..305cafdc9b 100644
--- a/target/arm/tcg/fp8_helper.c
+++ b/target/arm/tcg/fp8_helper.c
@@ -1005,3 +1005,46 @@ void HELPER(sme_fmop4a_hb)(void *vza, void *vzn, void
*vzm,
FP8MulContext ctx = fp8_mul_start(env, 0xf);
sme_mop4(vza, vzn, vzm, &ctx, desc, sizeof(float16), inner_fmop4a_hb);
}
+
+void HELPER(sme_ftmopa_hb)(void *vza, void *vzn, void *vzm, void *vzk,
+ CPUArchState *env, uint32_t desc)
+{
+ FP8MulContext ctx = fp8_mul_start(env, 0xf);
+ intptr_t oprsz = simd_maxsz(desc);
+ intptr_t dim = oprsz >> MO_16;
+ intptr_t index = simd_data(desc);
+ intptr_t ctrl_base = (index * oprsz) >> 1;
+ uint8_t *zn0 = vzn, *zn1 = vzn + sizeof(ARMVectorReg);
+ uint16_t *za = vza, *zm = vzm;
+ uint64_t *zk = vzk;
+
+ for (intptr_t row = 0; row < dim; row++) {
+ uint16_t *za_row = za + tile_vslice_offset(row);
+
+ for (intptr_t col = 0; col < dim; col++) {
+ uint16_t e2 = zm[H2(col)];
+ uint16_t *e3 = za_row + H2(col);
+ uint16_t e1 = 0;
+
+ /*
+ * Four control bits select two elements. The two elements
+ * may be non-contiguous, so assemble them locally into e1.
+ * Pseudo-code has a double loop running forward, with a
+ * test for (i < 2) to limit construction to 2 elements.
+ * Easier to run a single loop backward, shifting extra
+ * elements off the top of our uint16_t.
+ */
+ uint64_t this_ctrl = extractn(zk, ctrl_base + col * 4, 4);
+ for (int i = 3; i >= 0; i--) {
+ if (this_ctrl & (1 << i)) {
+ bool e = i & 1;
+ bool r = i & 2;
+ uint8_t *p = (r ? zn1 : zn0) + H1(2 * row + e);
+ e1 = (e1 << 8) | *p;
+ }
+ }
+
+ *e3 = f8dotadd_h(e1, e2, 2, *e3, &ctx);
+ }
+ }
+}
diff --git a/target/arm/tcg/translate-sme.c b/target/arm/tcg/translate-sme.c
index 43d1726972..395652f477 100644
--- a/target/arm/tcg/translate-sme.c
+++ b/target/arm/tcg/translate-sme.c
@@ -2167,3 +2167,15 @@ TRANS_FEAT(BFTMOPA_sh, aa64_sme_tmop, do_tmop_fp,
a, MO_32, FPST_ENV, gen_helper_sme_bftmopa_sh)
TRANS_FEAT(FTMOPA_sh, aa64_sme_tmop, do_tmop_fp,
a, MO_32, FPST_ENV, gen_helper_sme_ftmopa_sh)
+
+static bool do_tmop_fp8(DisasContext *s, arg_tmop *a, MemOp esz,
+ gen_helper_gvec_4_ptr *fn)
+{
+ if (!fpmr_access_check(s)) {
+ return true;
+ }
+ return do_tmop_fp(s, a, esz, FPST_ENV, fn);
+}
+
+TRANS_FEAT(FTMOPA_hb, aa64_sme_tmop_f8f16, do_tmop_fp8,
+ a, MO_16, gen_helper_sme_ftmopa_hb)
diff --git a/target/arm/tcg/sme.decode b/target/arm/tcg/sme.decode
index 5c453ea729..da6f4686d3 100644
--- a/target/arm/tcg/sme.decode
+++ b/target/arm/tcg/sme.decode
@@ -1148,3 +1148,5 @@ FTMOPA_ss 1000 0000 010 ..... 000 ... .... .. 00 ..
@tmop_o2
BFTMOPA_sh 1000 0001 010 ..... 000 ... .... .. 00 .. @tmop_o2
FTMOPA_sh 1000 0001 011 ..... 000 ... .... .. 00 .. @tmop_o2
+
+FTMOPA_hb 1000 0000 011 ..... 000 ... .... .. 100 . @tmop_o1
--
2.43.0
