On 7/13/2026 5:07 PM, Matheus Tavares Bernardino wrote:
This is currently unused by existing semihosting targets, but it will be used by hexagon. Signed-off-by: Matheus Tavares Bernardino <[email protected]> Signed-off-by: Brian Cain <[email protected]> ---
I suggest making it patch 06 in the series, right before you use in patch 7. You can even mention "next patch will use it" in the commit msg for extra clarity. As for the code: Reviewed-by: Daniel Henrique Barboza <[email protected]>
include/semihosting/common-semi.h | 1 + semihosting/arm-compat-semi.c | 1 + target/arm/common-semi-target.c | 4 ++++ target/riscv/common-semi-target.c | 4 ++++ 4 files changed, 10 insertions(+) diff --git a/include/semihosting/common-semi.h b/include/semihosting/common-semi.h index aa511a46f42..a11905ef4ef 100644 --- a/include/semihosting/common-semi.h +++ b/include/semihosting/common-semi.h @@ -37,6 +37,7 @@ void do_common_semihosting(CPUState *cs); uint64_t common_semi_arg(CPUState *cs, int argno); void common_semi_set_ret(CPUState *cs, uint64_t ret); +void common_semi_set_err(CPUState *cs, int err); bool is_64bit_semihosting(CPUArchState *env); bool common_semi_sys_exit_is_extended(CPUState *cs); uint64_t common_semi_stack_bottom(CPUState *cs); diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index 5e5f181b908..c54753f696f 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -237,6 +237,7 @@ static void common_semi_cb(CPUState *cs, uint64_t ret, int err) ts->swi_errno = err; #else syscall_err = err; + common_semi_set_err(cs, err); #endif } common_semi_set_ret(cs, ret); diff --git a/target/arm/common-semi-target.c b/target/arm/common-semi-target.c index 2b77ce9c17b..38d52deb3d6 100644 --- a/target/arm/common-semi-target.c +++ b/target/arm/common-semi-target.c @@ -34,6 +34,10 @@ void common_semi_set_ret(CPUState *cs, uint64_t ret) } }+void common_semi_set_err(CPUState *cs, int err)+{ +} + bool common_semi_sys_exit_is_extended(CPUState *cs) { return is_a64(cpu_env(cs)); diff --git a/target/riscv/common-semi-target.c b/target/riscv/common-semi-target.c index aeaeb88d536..38a00e160c3 100644 --- a/target/riscv/common-semi-target.c +++ b/target/riscv/common-semi-target.c @@ -26,6 +26,10 @@ void common_semi_set_ret(CPUState *cs, uint64_t ret) env->gpr[xA0] = ret; }+void common_semi_set_err(CPUState *cs, int err)+{ +} + bool is_64bit_semihosting(CPUArchState *env) { return riscv_cpu_mxl(env) != MXL_RV32;
