On 7/15/2026 11:56 AM, Brian Cain wrote: > From: Sid Manning <[email protected]> > > The Hexagon DSP requires an L2VIC to route up to 1024 > external interrupt sources through 4 VID output groups into > the core's 8 interrupt inputs. This device model implements > the register interface, interrupt steering, and edge/level > type handling needed by the sysemu machine models. > > Co-authored-by: Matheus Tavares Bernardino <[email protected]> > Co-authored-by: Damien Hedde <[email protected]> > Signed-off-by: Brian Cain <[email protected]> > --- > MAINTAINERS | 3 + > docs/devel/hexagon-l2vic.rst | 55 ++++ > docs/devel/index-internals.rst | 1 + > include/hw/intc/hex-l2vic.h | 87 ++++++ > target/hexagon/cpu.h | 2 + > hw/intc/hex-l2vic.c | 532 +++++++++++++++++++++++++++++++++ > target/hexagon/cpu.c | 2 + > target/hexagon/op_helper.c | 21 +- > hw/hexagon/Kconfig | 1 + > hw/intc/Kconfig | 3 + > hw/intc/meson.build | 2 + > hw/intc/trace-events | 4 + > 12 files changed, 712 insertions(+), 1 deletion(-) > create mode 100644 docs/devel/hexagon-l2vic.rst > create mode 100644 include/hw/intc/hex-l2vic.h > create mode 100644 hw/intc/hex-l2vic.c >
Reviewed-by: Pierrick Bouvier <[email protected]>
