Add the const qualifier to CPURISCVState when the argument is accessed without modification.
Signed-off-by: Philippe Mathieu-Daudé <[email protected]> --- target/riscv/cpu.h | 17 +++++++++-------- target/riscv/cpu.c | 2 +- 2 files changed, 10 insertions(+), 9 deletions(-) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index bb4c8563554..2333dcecd8a 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -636,7 +636,7 @@ int riscv_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_hviprio_index2irq(int index, int *out_irq, int *out_rdzero); uint8_t riscv_cpu_default_priority(int irq); -uint64_t riscv_cpu_all_pending(CPURISCVState *env); +uint64_t riscv_cpu_all_pending(const CPURISCVState *env); int riscv_cpu_mirq_pending(CPURISCVState *env); int riscv_cpu_sirq_pending(CPURISCVState *env); int riscv_cpu_vsirq_pending(CPURISCVState *env); @@ -746,7 +746,7 @@ FIELD(EXT_TB_FLAGS, BIG_ENDIAN, 33, 1) #ifdef TARGET_RISCV32 #define riscv_cpu_mxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_mxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_mxl(const CPURISCVState *env) { return env->misa_mxl; } @@ -759,7 +759,7 @@ static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env) } #if !defined(CONFIG_USER_ONLY) -static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) +static inline privilege_mode_t cpu_address_mode(const CPURISCVState *env) { privilege_mode_t mode = env->priv; @@ -769,7 +769,8 @@ static inline privilege_mode_t cpu_address_mode(CPURISCVState *env) return mode; } -static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode) +static inline RISCVMXL cpu_get_xl(const CPURISCVState *env, + privilege_mode_t mode) { RISCVMXL xl = env->misa_mxl; /* @@ -797,7 +798,7 @@ static inline RISCVMXL cpu_get_xl(CPURISCVState *env, privilege_mode_t mode) #if defined(TARGET_RISCV32) #define cpu_recompute_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) +static inline RISCVMXL cpu_recompute_xl(const CPURISCVState *env) { #if !defined(CONFIG_USER_ONLY) return cpu_get_xl(env, env->priv); @@ -810,7 +811,7 @@ static inline RISCVMXL cpu_recompute_xl(CPURISCVState *env) #if defined(TARGET_RISCV32) #define cpu_address_xl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL cpu_address_xl(CPURISCVState *env) +static inline RISCVMXL cpu_address_xl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->xl; @@ -822,7 +823,7 @@ static inline RISCVMXL cpu_address_xl(CPURISCVState *env) } #endif -static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) +static inline uint16_t riscv_cpu_xlen(const CPURISCVState *env) { return 16 << env->xl; } @@ -830,7 +831,7 @@ static inline uint16_t riscv_cpu_xlen(CPURISCVState *env) #ifdef TARGET_RISCV32 #define riscv_cpu_sxl(env) ((void)(env), MXL_RV32) #else -static inline RISCVMXL riscv_cpu_sxl(CPURISCVState *env) +static inline RISCVMXL riscv_cpu_sxl(const CPURISCVState *env) { #ifdef CONFIG_USER_ONLY return env->misa_mxl; diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 68f5a620402..a344daf62f8 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -908,7 +908,7 @@ int riscv_cpu_pending_to_irq(CPURISCVState *env, * using hvip bits 13:63 from HS-mode. Those are returned in * riscv_cpu_sirq_pending() and riscv_cpu_vsirq_pending(). */ -uint64_t riscv_cpu_all_pending(CPURISCVState *env) +uint64_t riscv_cpu_all_pending(const CPURISCVState *env) { uint32_t gein = get_field(env->hstatus, HSTATUS_VGEIN); uint64_t vsgein = (env->hgeip & (1ULL << gein)) ? MIP_VSEIP : 0; -- 2.53.0
