On 8/21/26 06:25, Peter Maydell wrote:
The "hint space" is a region of the encoding space which is defined
to NOP if not specified as an architected instruction, so that future
instructions can be added there which fall back to NOPs on older
CPUs. In the A32 encoding, this hint space was carved out of the MSR
(imm) insn by using the fact that a field_mask (bits [19:15]) of
0b0000 meant that an MSR (imm) would set no parts of the CPSR from
the immediate, so it was always NOP on existing CPUs.
For the T1 encoding, the hint space is in a range that used to UNDEF
in Armv5, and so the hint insns and the NOP region must all UNDEF
before v6T2. Rather than putting this check in the trans functions
for each hint insn and for the NOP space (which is a lot of places,
and awkward since those trans functions are often shared with the A64
and A32 encodings), put in a decode line that covers the whole space
which we check before any of the hints and which will explicitly
UNDEF if necessary.
Cc:[email protected]
Resolves:https://gitlab.com/qemu-project/qemu/-/work_items/4208
Signed-off-by: Peter Maydell<[email protected]>
---
target/arm/tcg/t16.decode | 3 +++
target/arm/tcg/translate.c | 18 ++++++++++++++++++
2 files changed, 21 insertions(+)
Reviewed-by: Richard Henderson <[email protected]>
r~
