On Mon, 24 Aug 2026 at 11:28, Peter Maydell <[email protected]> wrote: > > The GICv5 spec defines that an L2 IST is always aligned to its size, > by stating that bits [N:0] of the address are 0 where > N = 11 + (2 * L2SZ) > > We were missing this check, and only aligning by applying > R_L1_ISTE_L2_ADDR_MASK, so we would only enforce 4K alignment even if > the L2 IST was 16K or 64K. > > Add the missing masking of low bits. We already needed to calculate > the number of bits needed to index each byte in the L2 table, so add > it to the GICv5ISTConfig to save having to re-calculate it later. > > Signed-off-by: Peter Maydell <[email protected]> > --- > hw/intc/arm_gicv5.c | 6 ++++++ > include/hw/intc/arm_gicv5.h | 1 + > 2 files changed, 7 insertions(+) > > diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c > index cdc6c9d3466..20680a5c225 100644 > --- a/hw/intc/arm_gicv5.c > +++ b/hw/intc/arm_gicv5.c > @@ -595,6 +595,11 @@ static bool get_l2_iste_addr(GICv5Common *cs, const > GICv5ISTConfig *cfg, > return false; > } > l2_base = l1_iste & R_L1_ISTE_L2_ADDR_MASK; > + /* > + * The effective base address of the L2 table is always > + * aligned to the size of the L2 table. > + */ > + l2_base &= MAKE_64BIT_MASK(0, cfg->l2bits);
Here too we are missing a ~ . -- PMM
