Candence UART model is reserving 4 KiB for registers statically For other SoC models, the MMIO size may be not 4 KiB which would have overlapping sysbus regions in QEMU
This patch adds a property which allows other models to revise the MMIO size and it is 4 KiB by default Signed-off-by: Kuan-Jui Chiu <[email protected]> --- hw/char/cadence_uart.c | 8 ++++++-- include/hw/char/cadence_uart.h | 3 +++ 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index f57cad57a8..d83c71b877 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -541,6 +541,10 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp) { CadenceUARTState *s = CADENCE_UART(dev); + memory_region_init_io(&s->iomem, OBJECT(dev), &uart_ops, s, "uart", + s->mmio_size); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem); + s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL, fifo_trigger_update, s); @@ -561,8 +565,6 @@ static void cadence_uart_init(Object *obj) SysBusDevice *sbd = SYS_BUS_DEVICE(obj); CadenceUARTState *s = CADENCE_UART(obj); - memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000); - sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk", @@ -621,6 +623,8 @@ static const VMStateDescription vmstate_cadence_uart = { static const Property cadence_uart_properties[] = { DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), + DEFINE_PROP_SIZE("mmio-size", CadenceUARTState, mmio_size, + CADENCE_UART_MMIO_SIZE), }; static void cadence_uart_class_init(ObjectClass *klass, const void *data) diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h index 0f97e19112..585b00badf 100644 --- a/include/hw/char/cadence_uart.h +++ b/include/hw/char/cadence_uart.h @@ -31,6 +31,8 @@ #define CADENCE_UART_R_MAX (0x4C/4) +#define CADENCE_UART_MMIO_SIZE 0x1000 + #define TYPE_CADENCE_UART "cadence_uart" OBJECT_DECLARE_SIMPLE_TYPE(CadenceUARTState, CADENCE_UART) @@ -51,6 +53,7 @@ struct CadenceUARTState { qemu_irq irq; QEMUTimer *fifo_trigger_handle; Clock *refclk; + uint64_t mmio_size; }; #endif -- 2.34.1
