Re: [PATCH v4 4/8] hw/char/cadence_uart: Reserve MMIO with dynamic size

[Kuan-Jui Chiu]

Hi

Philippe Mathieu-Daudé 於 2026/8/26 下午 04:11 寫道:

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Hi,

On 26/8/26 09:46, Kuan-Jui Chiu wrote:

Candence UART model is reserving 4 KiB for registers statically
For other SoC models, the MMIO size may be not 4 KiB which would have
overlapping sysbus regions in QEMU

This patch adds a property which allows other models to revise the MMIO
size and it is 4 KiB by default

Signed-off-by: Kuan-Jui Chiu <kc...@axiado.com>
---
  hw/char/cadence_uart.c         | 8 ++++++--
  include/hw/char/cadence_uart.h | 3 +++
  2 files changed, 9 insertions(+), 2 deletions(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index f57cad57a8..d83c71b877 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c

@@ -541,6 +541,10 @@ static void cadence_uart_realize(DeviceState *dev, Error **errp)

  {
      CadenceUARTState *s = CADENCE_UART(dev);

+    memory_region_init_io(&s->iomem, OBJECT(dev), &uart_ops, s, "uart",
+                          s->mmio_size);
+    sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iomem);
+
      s->fifo_trigger_handle = timer_new_ns(QEMU_CLOCK_VIRTUAL,
                                            fifo_trigger_update, s);

@@ -561,8 +565,6 @@ static void cadence_uart_init(Object *obj)
      SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
      CadenceUARTState *s = CADENCE_UART(obj);

-    memory_region_init_io(&s->iomem, obj, &uart_ops, s, "uart", 0x1000);

Are we sure this size is even correct and not a copy/paste error?
We can clearly reduce it up to 0x80 (so far the last register
implemented is R_TTRIG at address 0x44).

No

It is 0x1000 since the first release of this model

Sure, I will change it to 0x80. It would be a simpler fix

-    sysbus_init_mmio(sbd, &s->iomem);
      sysbus_init_irq(sbd, &s->irq);

      s->refclk = qdev_init_clock_in(DEVICE(obj), "refclk",

@@ -621,6 +623,8 @@ static const VMStateDescription vmstate_cadence_uart = {

  static const Property cadence_uart_properties[] = {
      DEFINE_PROP_CHR("chardev", CadenceUARTState, chr),
+    DEFINE_PROP_SIZE("mmio-size", CadenceUARTState, mmio_size,
+                     CADENCE_UART_MMIO_SIZE),
  };