On 2026/08/26 10:38 AM, Chinmay Rath wrote:
> From: Nikhil Kumar Singh <[email protected]>
>
> Migrate load-and-reserve instructions (lbarx, lharx, lwarx, ldarx,
> lqarx) to decodetree using the X-form layout.
>
> A shared helper (do_load_locked) is introduced for standard-width
> variants, while LQARX is handled separately due to its 128-bit
> semantics and register pairing constraints.
>
> The implementation preserves legacy behavior, including:
> - Reservation granularity and overwrite semantics
> - Alignment requirements
> - Invalid instruction cases for LQARX
>
> Testing:
> - Verified TCG equivalence with legacy implementation
>
> Signed-off-by: Nikhil Kumar Singh <[email protected]>
> Reviewed-by: Glenn Miles <[email protected]>
> Signed-off-by: Chinmay Rath <[email protected]>
> ---
> target/ppc/insn32.decode | 7 +++
> target/ppc/translate.c | 124 +++++++++++++++++++--------------------
> 2 files changed, 69 insertions(+), 62 deletions(-)
>
> diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode
> index 342e65dadf..26948e08a7 100644
> --- a/target/ppc/insn32.decode
> +++ b/target/ppc/insn32.decode
> @@ -1309,6 +1309,13 @@ XVF64GERNN 111011 ... -- .... 0 ..... 11111010
> ..- @XX3_at xa=%xx_xa_pair
> ##Extend Sign Word and Shift Left Immediate XS-form
> EXTSWSLI 011111 ..... ..... ..... 110111101 . . @XS
>
> +## Load and Reserve Instructions
> +LBARX 011111 ..... ..... ..... 0000110100 . @X_rc
> +LHARX 011111 ..... ..... ..... 0001110100 . @X_rc
> +LWARX 011111 ..... ..... ..... 0000010100 . @X_rc
> +LDARX 011111 ..... ..... ..... 0001010100 . @X_rc
> +LQARX 011111 ..... ..... ..... 0100010100 . @X_rc
> +
> ## Vector Division Instructions
>
> VDIVSW 000100 ..... ..... ..... 00110001011 @VX
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index e627f48f9e..cc9287dcc5 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -2947,30 +2947,6 @@ static void gen_isync(DisasContext *ctx)
> ctx->base.is_jmp = DISAS_EXIT_UPDATE;
> }
>
> -static void gen_load_locked(DisasContext *ctx, MemOp memop)
> -{
> - TCGv gpr = cpu_gpr[rD(ctx->opcode)];
> - TCGv t0 = tcg_temp_new();
> -
> - gen_set_access_type(ctx, ACCESS_RES);
> - gen_addr_reg_index(ctx, t0);
> - tcg_gen_qemu_ld_tl(gpr, t0, ctx->mem_idx, DEF_MEMOP(memop) | MO_ALIGN);
> - tcg_gen_mov_tl(cpu_reserve, t0);
> - tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
> - tcg_gen_mov_tl(cpu_reserve_val, gpr);
> -}
> -
> -#define LARX(name, memop) \
> -static void gen_##name(DisasContext *ctx) \
> -{ \
> - gen_load_locked(ctx, memop); \
> -}
> -
> -/* lwarx */
> -LARX(lbarx, MO_UB)
> -LARX(lharx, MO_UW)
> -LARX(lwarx, MO_UL)
> -
> static void gen_fetch_inc_conditional(DisasContext *ctx, MemOp memop,
> TCGv EA, TCGCond cond, int addend)
> {
> @@ -3219,42 +3195,9 @@ STCX(sthcx_, MO_UW)
> STCX(stwcx_, MO_UL)
>
> #if defined(TARGET_PPC64)
> -/* ldarx */
> -LARX(ldarx, MO_UQ)
> /* stdcx. */
> STCX(stdcx_, MO_UQ)
>
> -/* lqarx */
> -static void gen_lqarx(DisasContext *ctx)
> -{
> - int rd = rD(ctx->opcode);
> - TCGv EA, hi, lo;
> - TCGv_i128 t16;
> -
> - if (unlikely((rd & 1) || (rd == rA(ctx->opcode)) ||
> - (rd == rB(ctx->opcode)))) {
> - gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> - return;
> - }
> -
> - gen_set_access_type(ctx, ACCESS_RES);
> - EA = tcg_temp_new();
> - gen_addr_reg_index(ctx, EA);
> -
> - /* Note that the low part is always in RD+1, even in LE mode. */
> - lo = cpu_gpr[rd + 1];
> - hi = cpu_gpr[rd];
> -
> - t16 = tcg_temp_new_i128();
> - tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx, DEF_MEMOP(MO_128 |
> MO_ALIGN));
> - tcg_gen_extr_i128_i64(lo, hi, t16);
> -
> - tcg_gen_mov_tl(cpu_reserve, EA);
> - tcg_gen_movi_tl(cpu_reserve_length, 16);
> - tcg_gen_st_tl(hi, tcg_env, offsetof(CPUPPCState, reserve_val));
> - tcg_gen_st_tl(lo, tcg_env, offsetof(CPUPPCState, reserve_val2));
> -}
> -
> /* stqcx. */
> static void gen_stqcx_(DisasContext *ctx)
> {
> @@ -5741,6 +5684,68 @@ static bool trans_EXTSWSLI(DisasContext *ctx, arg_XS
> *a)
> return true;
> }
>
> +/*
> + * Load-and-reserve core
> + */
> +static bool do_load_locked(DisasContext *ctx, arg_X_rc *a, MemOp memop)
> +{
> + TCGv EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
> + TCGv gpr = cpu_gpr[a->rt];
> +
> + gen_set_access_type(ctx, ACCESS_RES);
> +
> + tcg_gen_qemu_ld_tl(gpr, EA, ctx->mem_idx, memop | MO_ALIGN);
> +
> + tcg_gen_mov_tl(cpu_reserve, EA);
> + tcg_gen_movi_tl(cpu_reserve_length, memop_size(memop));
> +
> + tcg_gen_mov_tl(cpu_reserve_val, gpr);
> +
> + return true;
> +}
> +
> +TRANS_FLAGS2(ATOMIC_ISA206, LBARX, do_load_locked, DEF_MEMOP(MO_UB))
> +TRANS_FLAGS2(ATOMIC_ISA206, LHARX, do_load_locked, DEF_MEMOP(MO_UW))
> +TRANS(LWARX, do_load_locked, DEF_MEMOP(MO_UL))
> +TRANS64(LDARX, do_load_locked, DEF_MEMOP(MO_UQ))
> +
> +static bool trans_LQARX(DisasContext *ctx, arg_LQARX *a)
> +{
> + REQUIRE_64BIT(ctx);
> + REQUIRE_INSNS_FLAGS2(ctx, ISA207S);
The old GEN_HANDLER_E used PPC2_LSQ_ISA207, but the new code uses
PPC2_ISA207S . In the current QEMU CPU model set this makes no practical
difference — every CPU that sets PPC2_ISA207S also sets PPC2_LSQ_ISA207.
However, PPC2_LSQ_ISA207 is the precise flag for this feature and keeps
lqarx symmetric with its companion stqcx_ (line 5870) which correctly
continues to use PPC2_LSQ_ISA207. Please use REQUIRE_INSNS_FLAGS2(ctx,
LSQ_ISA207) for consistency and to guard against future CPU models that
may set these flags independently
> +#if defined(TARGET_PPC64)
> + TCGv EA;
> + TCGv_i128 t16;
> + /* Must use even register and avoid overlap */
> + if (unlikely((a->rt & 1) || (a->rt == a->ra) || (a->rt == a->rb))) {
> + gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
> + return true;
> + }
> +
> + gen_set_access_type(ctx, ACCESS_RES);
> + EA = do_ea_calc(ctx, a->ra, cpu_gpr[a->rb]);
> + t16 = tcg_temp_new_i128();
> +
> + tcg_gen_qemu_ld_i128(t16, EA, ctx->mem_idx,
> + DEF_MEMOP(MO_128 | MO_ALIGN));
> +
> + tcg_gen_extr_i128_i64(cpu_gpr[a->rt + 1],
> + cpu_gpr[a->rt],
> + t16);
> +
> + tcg_gen_mov_tl(cpu_reserve, EA);
> + tcg_gen_movi_tl(cpu_reserve_length, 16);
> +
> + tcg_gen_st_i64(cpu_gpr[a->rt],
> + tcg_env, offsetof(CPUPPCState, reserve_val));
All these multi-line calls can be collapsed to single lines — they are
within 80 characters respectively and fit within the 80-column limit.
The only exception is tcg_gen_st_i64(..., reserve_val2) at 85 chars,
which legitimately needs wrapping. The unnecessary line splits add
visual noise without any readability benefit.
> + tcg_gen_st_i64(cpu_gpr[a->rt + 1],
> + tcg_env, offsetof(CPUPPCState, reserve_val2));
> +#else
> + qemu_build_not_reached();
> +#endif
> + return true;
> +}
> +
> #include "translate/fixedpoint-impl.c.inc"
>
> #include "translate/fp-impl.c.inc"
> @@ -5853,9 +5858,6 @@ GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001,
> PPC_STRING),
> GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
> GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
> GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
> -GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> -GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> -GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
> GEN_HANDLER_E(lwat, 0x1F, 0x06, 0x12, 0x00000001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(stwat, 0x1F, 0x06, 0x16, 0x00000001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
> @@ -5864,8 +5866,6 @@ GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04,
> 0x00000000, PPC_RES),
> #if defined(TARGET_PPC64)
> GEN_HANDLER_E(ldat, 0x1F, 0x06, 0x13, 0x00000001, PPC_NONE, PPC2_ISA300),
> GEN_HANDLER_E(stdat, 0x1F, 0x06, 0x17, 0x00000001, PPC_NONE, PPC2_ISA300),
> -GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
> -GEN_HANDLER_E(lqarx, 0x1F, 0x14, 0x08, 0, PPC_NONE, PPC2_LSQ_ISA207),
> GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
> GEN_HANDLER_E(stqcx_, 0x1F, 0x16, 0x05, 0, PPC_NONE, PPC2_LSQ_ISA207),
> #endif
> --
> 2.55.0
>
