The RISCVHartArrayState member is named soc, but it's an array of cpus, not the entire SoC. Use cpus instead as an accurate description of the hart array.
Signed-off-by: Joel Stanley <[email protected]> --- include/hw/riscv/tt_atlantis.h | 2 +- hw/riscv/tt_atlantis.c | 34 +++++++++++++++++----------------- 2 files changed, 18 insertions(+), 18 deletions(-) diff --git a/include/hw/riscv/tt_atlantis.h b/include/hw/riscv/tt_atlantis.h index d0cca3b02424..642490d21743 100644 --- a/include/hw/riscv/tt_atlantis.h +++ b/include/hw/riscv/tt_atlantis.h @@ -29,7 +29,7 @@ struct TTAtlantisState { Notifier machine_done; const MemMapEntry *memmap; - RISCVHartArrayState soc; + RISCVHartArrayState cpus; DeviceState *irqchip; DesignWareI2CState i2c[TT_ATL_NUM_I2C]; UnimplementedDeviceState uart1; diff --git a/hw/riscv/tt_atlantis.c b/hw/riscv/tt_atlantis.c index 127c89be4f60..35b3be072a06 100644 --- a/hw/riscv/tt_atlantis.c +++ b/hw/riscv/tt_atlantis.c @@ -112,13 +112,13 @@ static void create_fdt_aclint(TTAtlantisState *s, uint32_t *intc_phandles) uint32_t aclint_cells_size; hwaddr addr; - aclint_mtimer_cells = g_new0(uint32_t, s->soc.num_harts * 2); + aclint_mtimer_cells = g_new0(uint32_t, s->cpus.num_harts * 2); - for (int cpu = 0; cpu < s->soc.num_harts; cpu++) { + for (int cpu = 0; cpu < s->cpus.num_harts; cpu++) { aclint_mtimer_cells[cpu * 2 + 0] = cpu_to_be32(intc_phandles[cpu]); aclint_mtimer_cells[cpu * 2 + 1] = cpu_to_be32(IRQ_M_TIMER); } - aclint_cells_size = s->soc.num_harts * sizeof(uint32_t) * 2; + aclint_cells_size = s->cpus.num_harts * sizeof(uint32_t) * 2; addr = s->memmap[TT_ATL_ACLINT].base; @@ -210,7 +210,7 @@ static void create_fdt_pmu(TTAtlantisState *s) { char pmu_name[] = "/pmu"; void *fdt = MACHINE(s)->fdt; - RISCVCPU *hart = &s->soc.harts[0]; + RISCVCPU *hart = &s->cpus.harts[0]; qemu_fdt_add_subnode(fdt, pmu_name); qemu_fdt_setprop_string(fdt, pmu_name, "compatible", "riscv,pmu"); @@ -227,8 +227,8 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, fdt_create_cpu_socket_subnode(fdt, TT_ACLINT_TIMEBASE_FREQ); - create_fdt_socket_cpus(fdt, s->soc.harts, 0, s->soc.num_harts, - s->soc.hartid_base, &fdt_phandle, intc_phandles, + create_fdt_socket_cpus(fdt, s->cpus.harts, 0, s->cpus.num_harts, + s->cpus.hartid_base, &fdt_phandle, intc_phandles, false, false); create_fdt_memory(s); @@ -252,13 +252,13 @@ static void create_fdt_cpu(TTAtlantisState *s, const MemMapEntry *memmap, create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_MAPLIC], msi_m_phandle, intc_phandles, aplic_m_phandle, aplic_s_phandle, - IRQ_M_EXT, s->soc.num_harts); + IRQ_M_EXT, s->cpus.num_harts); /* S-level APLIC node */ create_fdt_one_aplic(fdt, &s->memmap[TT_ATL_SAPLIC], imsic_s_phandle, intc_phandles, aplic_s_phandle, 0, - IRQ_S_EXT, s->soc.num_harts); + IRQ_S_EXT, s->cpus.num_harts); } static void create_fdt_uart(void *fdt, const MemMapEntry *mem, int irq, @@ -429,7 +429,7 @@ static void tt_atlantis_machine_done(Notifier *notifier, void *data) hwaddr start_addr = s->memmap[TT_ATL_DDR_LO].base; hwaddr mem_size; target_ulong firmware_end_addr, kernel_start_addr; - const char *firmware_name = riscv_default_firmware_name(&s->soc); + const char *firmware_name = riscv_default_firmware_name(&s->cpus); uint64_t fdt_load_addr; uint64_t kernel_entry; RISCVBootInfo boot_info; @@ -446,7 +446,7 @@ static void tt_atlantis_machine_done(Notifier *notifier, void *data) if (mem_size > s->memmap[TT_ATL_DDR_LO].size) { mem_size = s->memmap[TT_ATL_DDR_LO].size; } - riscv_boot_info_init_discontig_mem(&boot_info, &s->soc, + riscv_boot_info_init_discontig_mem(&boot_info, &s->cpus, s->memmap[TT_ATL_DDR_LO].base, mem_size); @@ -476,7 +476,7 @@ static void tt_atlantis_machine_done(Notifier *notifier, void *data) riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ - riscv_setup_rom_reset_vec(machine, &s->soc, start_addr, + riscv_setup_rom_reset_vec(machine, &s->cpus, start_addr, s->memmap[TT_ATL_BOOTROM].base, s->memmap[TT_ATL_BOOTROM].size, kernel_entry, @@ -496,18 +496,18 @@ static void tt_atlantis_machine_init(MachineState *machine) s->memmap = tt_atlantis_memmap; - object_initialize_child(OBJECT(machine), "soc", &s->soc, + object_initialize_child(OBJECT(machine), "soc", &s->cpus, TYPE_RISCV_HART_ARRAY); - object_property_set_str(OBJECT(&s->soc), "cpu-type", machine->cpu_type, + object_property_set_str(OBJECT(&s->cpus), "cpu-type", machine->cpu_type, &error_abort); - object_property_set_int(OBJECT(&s->soc), "hartid-base", 0, + object_property_set_int(OBJECT(&s->cpus), "hartid-base", 0, &error_abort); - object_property_set_int(OBJECT(&s->soc), "num-harts", hart_count, + object_property_set_int(OBJECT(&s->cpus), "num-harts", hart_count, &error_abort); - object_property_set_int(OBJECT(&s->soc), "resetvec", + object_property_set_int(OBJECT(&s->cpus), "resetvec", s->memmap[TT_ATL_BOOTROM].base, &error_abort); - sysbus_realize(SYS_BUS_DEVICE(&s->soc), &error_fatal); + sysbus_realize(SYS_BUS_DEVICE(&s->cpus), &error_fatal); s->irqchip = riscv_create_aia(system_memory, true, TT_IMSIC_GUESTS, -- 2.47.3
